testsuite/synth: add tests for individual associations.

8 files changed, 185 insertions, 0 deletions

diff --git a/testsuite/synth/iassoc01/iassoc01.vhdl b/testsuite/synth/iassoc01/iassoc01.vhdl
new file mode 100644
index 000000000..6a0a46bd0
--- /dev/null
+++ b/testsuite/synth/iassoc01/iassoc01.vhdl
@@ -0,0 +1,22 @@
+use work.pkg.all;
+
+entity riassoc01 is
+  port (v : nat_rec;
+        res : out natural);
+end riassoc01;
+
+architecture behav of riassoc01 is
+begin
+  res <= v.a + v.b;
+end behav;
+
+entity iassoc01 is
+  port (a, b : natural;
+        res : out natural);
+end iassoc01;
+
+architecture behav of iassoc01 is
+begin
+  inst : entity work.riassoc01
+    port map (v.a => a, v.b => b, res => res);
+end behav;
diff --git a/testsuite/synth/iassoc01/iassoc02.vhdl b/testsuite/synth/iassoc01/iassoc02.vhdl
new file mode 100644
index 000000000..69064375a
--- /dev/null
+++ b/testsuite/synth/iassoc01/iassoc02.vhdl
@@ -0,0 +1,23 @@
+use work.pkg.all;
+
+entity riassoc02 is
+  port (v : natural;
+        res : out nat_rec);
+end riassoc02;
+
+architecture behav of riassoc02 is
+begin
+  res.a <= v + 1;
+  res.b <= v + 2;
+end behav;
+
+entity iassoc02 is
+  port (v : natural;
+        a, b : out natural);
+end iassoc02;
+
+architecture behav of iassoc02 is
+begin
+  inst : entity work.riassoc02
+    port map (v => v, res.a => a, res.b => b);
+end behav;
diff --git a/testsuite/synth/iassoc01/iassoc03.vhdl b/testsuite/synth/iassoc01/iassoc03.vhdl
new file mode 100644
index 000000000..f2284b86b
--- /dev/null
+++ b/testsuite/synth/iassoc01/iassoc03.vhdl
@@ -0,0 +1,30 @@
+use work.pkg.all;
+
+entity riassoc03 is
+  port (v : nat_arr (1 to 2);
+        res : out natural);
+end riassoc03;
+
+architecture behav of riassoc03 is
+begin
+  process (v)
+    variable t : natural;
+  begin
+    t := 0;
+    for i in v'range loop
+      t := t + v (i);
+    end loop;
+    res <= t;
+  end process;
+end behav;
+
+entity iassoc03 is
+  port (a, b : natural;
+        res : out natural);
+end iassoc03;
+
+architecture behav of iassoc03 is
+begin
+  inst : entity work.riassoc03
+    port map (v (1) => a, v (2) => b, res => res);
+end behav;
diff --git a/testsuite/synth/iassoc01/pkg.vhdl b/testsuite/synth/iassoc01/pkg.vhdl
new file mode 100644
index 000000000..06b0a9718
--- /dev/null
+++ b/testsuite/synth/iassoc01/pkg.vhdl
@@ -0,0 +1,7 @@
+package pkg is
+  type nat_rec is record
+    a, b : natural;
+  end record;
+
+  type nat_arr is array (natural range <>) of natural;
+end pkg;
diff --git a/testsuite/synth/iassoc01/tb_iassoc01.vhdl b/testsuite/synth/iassoc01/tb_iassoc01.vhdl
new file mode 100644
index 000000000..0fcb42712
--- /dev/null
+++ b/testsuite/synth/iassoc01/tb_iassoc01.vhdl
@@ -0,0 +1,29 @@
+entity tb_iassoc01 is
+end tb_iassoc01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_iassoc01 is
+  signal a : natural;
+  signal b : natural;
+  signal res : natural;
+begin
+  dut: entity work.iassoc01
+    port map (a, b, res);
+
+  process
+  begin
+    a <= 1;
+    b <= 5;
+    wait for 1 ns;
+    assert res = 6 severity failure;
+
+    a <= 197;
+    b <= 203;
+    wait for 1 ns;
+    assert res = 400 severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/iassoc01/tb_iassoc02.vhdl b/testsuite/synth/iassoc01/tb_iassoc02.vhdl
new file mode 100644
index 000000000..36cc2eba0
--- /dev/null
+++ b/testsuite/synth/iassoc01/tb_iassoc02.vhdl
@@ -0,0 +1,29 @@
+entity tb_iassoc02 is
+end tb_iassoc02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_iassoc02 is
+  signal a : natural;
+  signal b : natural;
+  signal v : natural;
+begin
+  dut: entity work.iassoc02
+    port map (v, a, b);
+
+  process
+  begin
+    v <= 5;
+    wait for 1 ns;
+    assert a = 6 severity failure;
+    assert b = 7 severity failure;
+
+    v <= 203;
+    wait for 1 ns;
+    assert a = 204 severity failure;
+    assert b = 205 severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/iassoc01/tb_iassoc03.vhdl b/testsuite/synth/iassoc01/tb_iassoc03.vhdl
new file mode 100644
index 000000000..8bcaf360f
--- /dev/null
+++ b/testsuite/synth/iassoc01/tb_iassoc03.vhdl
@@ -0,0 +1,29 @@
+entity tb_iassoc03 is
+end tb_iassoc03;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_iassoc03 is
+  signal a : natural;
+  signal b : natural;
+  signal res : natural;
+begin
+  dut: entity work.iassoc03
+    port map (a, b, res);
+
+  process
+  begin
+    a <= 1;
+    b <= 5;
+    wait for 1 ns;
+    assert res = 6 severity failure;
+
+    a <= 197;
+    b <= 203;
+    wait for 1 ns;
+    assert res = 400 severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/iassoc01/testsuite.sh b/testsuite/synth/iassoc01/testsuite.sh
new file mode 100755
index 000000000..15f76c252
--- /dev/null
+++ b/testsuite/synth/iassoc01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in iassoc01 iassoc02 iassoc03; do
+    analyze pkg.vhdl $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth pkg.vhdl $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"