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author | Tristan Gingold <tgingold@free.fr> | 2020-02-29 11:16:01 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-02-29 11:16:01 +0100 |
commit | 3d2b4e54964242203e77cd0abfdc9c45c4cc3132 (patch) | |
tree | 015a8c6bc2002cc823fb791b03d330471edc5f67 /testsuite | |
parent | 19b544a0b3a1e19dcba07a776c90d176d7dd8f6f (diff) | |
download | ghdl-3d2b4e54964242203e77cd0abfdc9c45c4cc3132.tar.gz ghdl-3d2b4e54964242203e77cd0abfdc9c45c4cc3132.tar.bz2 ghdl-3d2b4e54964242203e77cd0abfdc9c45c4cc3132.zip |
testsuite/synth: add a reproducer for tgingold/ghdlsynth-beta#87
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/synth/synth87/repro01.vhdl | 23 | ||||
-rw-r--r-- | testsuite/synth/synth87/tb_repro01.vhdl | 31 | ||||
-rwxr-xr-x | testsuite/synth/synth87/testsuite.sh | 16 |
3 files changed, 70 insertions, 0 deletions
diff --git a/testsuite/synth/synth87/repro01.vhdl b/testsuite/synth/synth87/repro01.vhdl new file mode 100644 index 000000000..82a04e722 --- /dev/null +++ b/testsuite/synth/synth87/repro01.vhdl @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity repro01 is + port (a, b, c : in std_logic; + z : out std_logic); +end repro01; + +architecture behav of repro01 is + subtype logic is std_logic; + + type my_rec is record + a : std_logic_vector(7 downto 0); + end record; + subtype my_rec2 is my_rec; +begin + process(A, B, C) + variable temp : logic; + begin + temp := A and B; + Z <= temp or C; + end process; +end behav; diff --git a/testsuite/synth/synth87/tb_repro01.vhdl b/testsuite/synth/synth87/tb_repro01.vhdl new file mode 100644 index 000000000..e12ecbaa2 --- /dev/null +++ b/testsuite/synth/synth87/tb_repro01.vhdl @@ -0,0 +1,31 @@ +entity tb_repro01 is +end tb_repro01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_repro01 is + signal a : std_logic; + signal b : std_logic; + signal c : std_logic; + signal z : std_logic; +begin + dut: entity work.repro01 + port map (a, b, c, z); + + process + constant av : std_logic_vector := b"1101"; + constant bv : std_logic_vector := b"0111"; + constant cv : std_logic_vector := b"0011"; + constant zv : std_logic_vector := b"0111"; + begin + for i in av'range loop + a <= av (i); + b <= bv (i); + c <= cv (i); + wait for 1 ns; + assert z = zv(i) severity failure; + end loop; + wait; + end process; +end behav; diff --git a/testsuite/synth/synth87/testsuite.sh b/testsuite/synth/synth87/testsuite.sh new file mode 100755 index 000000000..0c9f3ac76 --- /dev/null +++ b/testsuite/synth/synth87/testsuite.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in repro01; do + analyze $t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean + + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl tb_$t.vhdl + elab_simulate tb_$t --ieee-asserts=disable-at-0 + clean +done + +echo "Test successful" |