testsuite: add a test for #1018

2 files changed, 36 insertions, 0 deletions

diff --git a/testsuite/synth/issue1018/test.vhdl b/testsuite/synth/issue1018/test.vhdl
new file mode 100644
index 000000000..0490fb4e6
--- /dev/null
+++ b/testsuite/synth/issue1018/test.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+    port(
+        clk     : in std_logic;
+        wr_addr : in std_logic_vector(0 downto 0);
+        wr_data : in std_logic_vector(7 downto 0)
+        );
+end test;
+
+architecture rtl of test is
+    type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
+    signal ram : ram_type := (others => (others => '0'));
+begin
+    process(clk)
+        variable widx : integer range 0 to 1;
+    begin
+        if rising_edge(clk) then
+            widx := to_integer(unsigned(wr_addr));
+            ram(widx) <= wr_data;
+        end if;
+    end process;
+end;
diff --git a/testsuite/synth/issue1018/testsuite.sh b/testsuite/synth/issue1018/testsuite.sh
new file mode 100755
index 000000000..45e08609a
--- /dev/null
+++ b/testsuite/synth/issue1018/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in test ; do
+    synth -de $t.vhdl -e > syn_$t.vhdl
+    analyze syn_$t.vhdl
+    clean
+done
+
+echo "Test successful"