testsuite/gna: add a test for #1657

3 files changed, 65 insertions, 0 deletions

diff --git a/testsuite/gna/issue1657/repro.vhdl b/testsuite/gna/issue1657/repro.vhdl
new file mode 100644
index 000000000..17418dd86
--- /dev/null
+++ b/testsuite/gna/issue1657/repro.vhdl
@@ -0,0 +1,25 @@
+entity repro is
+end;
+
+architecture rtl of repro is
+begin
+  Test_Proc: process
+    type bit_vector_array is array(natural range <>) of bit_vector;
+    variable v : bit_vector_array(0 to 3)(7 downto 0) :=
+      (others => (others => '0'));
+    begin
+      v := v(1 to 3) & bit_vector'(x"FF");
+
+      for i in v'range loop
+        report "V(" & natural'image(i) & ") = " & to_string (v(i));
+      end loop;
+
+      assert V(0) = x"00" severity failure;
+      assert V(1) = x"00" severity failure;
+      assert V(2) = x"00" severity failure;
+      assert V(3) = x"FF" severity failure;
+
+      report "TESTING" severity note;
+      wait;
+    end process;
+end architecture rtl;
diff --git a/testsuite/gna/issue1657/test_entity.vhdl b/testsuite/gna/issue1657/test_entity.vhdl
new file mode 100644
index 000000000..96f0dc58d
--- /dev/null
+++ b/testsuite/gna/issue1657/test_entity.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use std.env.finish;
+
+
+entity test is
+end entity test;
+
+architecture rtl of test is
+    
+    type std_logic_vector_array is array(natural range <>) of std_logic_vector;
+    signal test_sig : std_logic_vector_array(0 to 3)(7 downto 0) := (others => (others => '0'));
+
+begin
+    
+    Test_Proc: process
+    begin
+        for i in 0 to 15 loop
+            test_sig <= test_sig(1 to 3) & std_logic_vector'(x"FF");
+            wait for 1 us;
+            report "TESTING" severity note;
+        end loop;    
+        finish;
+    end process;
+
+end architecture rtl;
\ No newline at end of file
diff --git a/testsuite/gna/issue1657/testsuite.sh b/testsuite/gna/issue1657/testsuite.sh
new file mode 100755
index 000000000..5bc68fbe4
--- /dev/null
+++ b/testsuite/gna/issue1657/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze repro.vhdl
+elab_simulate repro
+
+analyze test_entity.vhdl
+elab_simulate test
+
+clean
+
+echo "Test successful"