diff options
author | Tristan Gingold <tgingold@free.fr> | 2016-02-13 18:03:20 +0100 |
---|---|---|
committer | Tristan Gingold <tgingold@free.fr> | 2016-02-14 13:52:34 +0100 |
commit | 32d422d2f5d002354aeaf111ce484b6665a5c9d5 (patch) | |
tree | 6c9cb25eca0e42366706aaaec126595182940c23 /testsuite | |
parent | ace70f3cc4d5ac8d5fb7e02e96d5b3187319e520 (diff) | |
download | ghdl-32d422d2f5d002354aeaf111ce484b6665a5c9d5.tar.gz ghdl-32d422d2f5d002354aeaf111ce484b6665a5c9d5.tar.bz2 ghdl-32d422d2f5d002354aeaf111ce484b6665a5c9d5.zip |
Rewrite cover tests.
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/gna/ticket19/psl_test_cover.vhd | 2 | ||||
-rw-r--r-- | testsuite/gna/ticket19/psl_test_cover2.vhd | 2 | ||||
-rw-r--r-- | testsuite/gna/ticket19/psl_test_cover3.vhd | 2 | ||||
-rw-r--r-- | testsuite/gna/ticket92/cover_report1.vhd | 57 | ||||
-rw-r--r-- | testsuite/gna/ticket92/cover_report2.vhd | 59 | ||||
-rw-r--r-- | testsuite/gna/ticket92/cover_report3.vhd | 59 | ||||
-rwxr-xr-x | testsuite/gna/ticket92/testsuite.sh | 13 |
7 files changed, 189 insertions, 5 deletions
diff --git a/testsuite/gna/ticket19/psl_test_cover.vhd b/testsuite/gna/ticket19/psl_test_cover.vhd index 9fa73ec05..821529248 100644 --- a/testsuite/gna/ticket19/psl_test_cover.vhd +++ b/testsuite/gna/ticket19/psl_test_cover.vhd @@ -47,7 +47,7 @@ begin -- psl default clock is rising_edge(s_clk); -- cover directive seems not supported (ignored by GHDL) - -- psl cover always (s_write -> not(s_read)); + -- psl cover { s_write ; not(s_read)}; end architecture test; diff --git a/testsuite/gna/ticket19/psl_test_cover2.vhd b/testsuite/gna/ticket19/psl_test_cover2.vhd index 000657d4c..5858e5168 100644 --- a/testsuite/gna/ticket19/psl_test_cover2.vhd +++ b/testsuite/gna/ticket19/psl_test_cover2.vhd @@ -54,7 +54,7 @@ begin -- psl default clock is rising_edge(s_clk); -- cover directive seems not supported (ignored by GHDL) - -- psl cover always (s_write -> not(s_read)); + -- psl cover {s_write ; not(s_read)}; end architecture test; diff --git a/testsuite/gna/ticket19/psl_test_cover3.vhd b/testsuite/gna/ticket19/psl_test_cover3.vhd index 260a47965..bf4a4ef64 100644 --- a/testsuite/gna/ticket19/psl_test_cover3.vhd +++ b/testsuite/gna/ticket19/psl_test_cover3.vhd @@ -47,7 +47,7 @@ begin -- psl default clock is rising_edge(s_clk); -- cover directive seems not supported (ignored by GHDL) - -- psl cover always (s_write -> not(s_read)); + -- psl cover { s_write ; not(s_read)}; end architecture test; diff --git a/testsuite/gna/ticket92/cover_report1.vhd b/testsuite/gna/ticket92/cover_report1.vhd new file mode 100644 index 000000000..4b436a5fd --- /dev/null +++ b/testsuite/gna/ticket92/cover_report1.vhd @@ -0,0 +1,57 @@ +library ieee; + use ieee.std_logic_1164.all; + +library std; + use std.env.all; + + + +entity cover_report1 is +end entity cover_report1; + +architecture test of cover_report1 is + + + signal s_a : std_logic; + signal s_b : std_logic; + signal s_c : std_logic; + signal s_clk : std_logic := '0'; + + +begin + + + s_clk <= not(s_clk) after 5 ns; + + + process is + begin + s_a <= '0'; + s_b <= '0'; + s_c <= '0'; + wait until rising_edge(s_clk); + s_a <= '1'; + wait until rising_edge(s_clk); + s_a <= '0'; + --s_b <= '1'; + wait until rising_edge(s_clk); + s_b <= '0'; + wait until rising_edge(s_clk); + s_c <= '0'; + stop(0); + end process; + + + -- psl default clock is rising_edge(s_clk); + -- + -- psl sequence test_p is {s_a; s_b}; + -- + -- DOES WORK + -- -- psl TEST : cover test_p; + -- + -- DOESN'T WORK: + -- psl cover test_p report "Covered"; + -- - psl assert eventually! test_p; + + +end architecture test; diff --git a/testsuite/gna/ticket92/cover_report2.vhd b/testsuite/gna/ticket92/cover_report2.vhd new file mode 100644 index 000000000..9e4050372 --- /dev/null +++ b/testsuite/gna/ticket92/cover_report2.vhd @@ -0,0 +1,59 @@ +library ieee; + use ieee.std_logic_1164.all; + +library std; + use std.env.all; + + + +entity cover_report2 is +end entity cover_report2; + + + +architecture test of cover_report2 is + + + signal s_a : std_logic; + signal s_b : std_logic; + signal s_c : std_logic; + signal s_clk : std_logic := '0'; + + +begin + + + s_clk <= not(s_clk) after 5 ns; + + + process is + begin + s_a <= '0'; + s_b <= '0'; + s_c <= '0'; + wait until rising_edge(s_clk); + s_a <= '1'; + wait until rising_edge(s_clk); + s_a <= '0'; + s_b <= '1'; + wait until rising_edge(s_clk); + s_b <= '0'; + s_c <= '1'; + wait until rising_edge(s_clk); + s_c <= '0'; + stop(0); + end process; + + + -- psl default clock is rising_edge(s_clk); + -- + -- psl sequence test_p is {s_a; s_b}; + -- + -- DOES WORK + -- -- psl TEST : cover test_p; + -- + -- DOESN'T WORK: + -- psl cover test_p report "Covered"; + + +end architecture test; diff --git a/testsuite/gna/ticket92/cover_report3.vhd b/testsuite/gna/ticket92/cover_report3.vhd new file mode 100644 index 000000000..e9393b056 --- /dev/null +++ b/testsuite/gna/ticket92/cover_report3.vhd @@ -0,0 +1,59 @@ +library ieee; + use ieee.std_logic_1164.all; + +library std; + use std.env.all; + + + +entity cover_report3 is +end entity cover_report3; + + + +architecture test of cover_report3 is + + + signal s_a : std_logic; + signal s_b : std_logic; + signal s_c : std_logic; + signal s_clk : std_logic := '0'; + + +begin + + + s_clk <= not(s_clk) after 5 ns; + + + process is + begin + s_a <= '0'; + s_b <= '0'; + s_c <= '0'; + wait until rising_edge(s_clk); + s_a <= '1'; + wait until rising_edge(s_clk); + s_a <= '0'; + s_b <= '1'; + wait until rising_edge(s_clk); + s_b <= '0'; + s_c <= '1'; + wait until rising_edge(s_clk); + s_c <= '0'; + stop(0); + end process; + + + -- psl default clock is rising_edge(s_clk); + -- + -- psl sequence test_p is ({s_a; s_b}); + -- + -- DOES WORK + -- -- psl TEST : cover test_p; + -- + -- DOESN'T WORK: + -- psl cover test_p report "Covered"; + + +end architecture test; diff --git a/testsuite/gna/ticket92/testsuite.sh b/testsuite/gna/ticket92/testsuite.sh index 8a76a9833..be808afa2 100755 --- a/testsuite/gna/ticket92/testsuite.sh +++ b/testsuite/gna/ticket92/testsuite.sh @@ -4,8 +4,17 @@ GHDL_STD_FLAGS="--std=08 -fpsl" -analyze cover_report.vhd -elab_simulate cover_report +analyze cover_report2.vhd +elab_simulate cover_report2 + +# Submitted case was not correct. +analyze_failure cover_report.vhd + +# Parenthesis not allowed in sequences. +analyze_failure cover_report3.vhd + +analyze cover_report1.vhd +elab_simulate cover_report1 clean echo "Test successful" |