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authorTristan Gingold <tgingold@free.fr>2021-09-07 21:25:25 +0200
committerTristan Gingold <tgingold@free.fr>2021-09-07 21:25:25 +0200
commit265cc22a5ca65c552d7e9c2b55f800787254c687 (patch)
tree35742ed4f2308103696d431629d1c7a561e8a5bf /testsuite
parentc6243752a7b0c64dbd798bb1c45d4f537be77980 (diff)
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testsuite/gna: add a test for #916
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/gna/issue916/dut.vhdl24
-rwxr-xr-xtestsuite/gna/issue916/testsuite.sh11
2 files changed, 35 insertions, 0 deletions
diff --git a/testsuite/gna/issue916/dut.vhdl b/testsuite/gna/issue916/dut.vhdl
new file mode 100644
index 000000000..8d11c0b42
--- /dev/null
+++ b/testsuite/gna/issue916/dut.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+entity avmm_csr is
+ Port (
+ reg_i : in std_ulogic_vector
+ );
+end avmm_csr;
+architecture rtl of avmm_csr is
+begin
+end rtl;
+
+
+library ieee;
+use ieee.numeric_std_unsigned.all;
+entity dut is
+end entity dut;
+architecture rtl of dut is
+ signal int : natural;
+begin
+ inst : entity work.avmm_csr
+ port map (
+ reg_i => to_slv(int, 2)
+ );
+end architecture rtl;
diff --git a/testsuite/gna/issue916/testsuite.sh b/testsuite/gna/issue916/testsuite.sh
new file mode 100755
index 000000000..0a831521f
--- /dev/null
+++ b/testsuite/gna/issue916/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze dut.vhdl
+elab_simulate dut
+
+clean
+
+echo "Test successful"