testsuite/gna: add tests for #756

3 files changed, 59 insertions, 0 deletions

diff --git a/testsuite/gna/issue756/test_entity.vhdl b/testsuite/gna/issue756/test_entity.vhdl
new file mode 100644
index 000000000..b2be7a88b
--- /dev/null
+++ b/testsuite/gna/issue756/test_entity.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all,
+    ieee.numeric_std.all;
+
+entity test_entity is
+	generic (
+		ARR_SIZE : natural := 4;
+		VECTOR_SIZE : natural := 7
+	);
+end test_entity;
+
+architecture behaviour of test_entity is
+	type type_simple_array is array(natural range <>) of std_logic_vector(7 downto 0);
+	type type_multi_array is array(natural range <>) of std_logic_vector;
+
+	signal sig_simple : type_simple_array(0 to ARR_SIZE);
+	signal sig_multi_1 : type_multi_array(0 to 4)(7 downto 0);
+	signal sig_multi_2 : type_multi_array(0 to 4)(VECTOR_SIZE downto 0);
+
+	-- erroring instruction below
+	signal sig_multi_3 : type_multi_array(0 to ARR_SIZE)(7 downto 0);
+begin
+end behaviour;
diff --git a/testsuite/gna/issue756/test_entity1.vhdl b/testsuite/gna/issue756/test_entity1.vhdl
new file mode 100644
index 000000000..ba5191065
--- /dev/null
+++ b/testsuite/gna/issue756/test_entity1.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test_entity is
+	generic (
+		n : natural := 5;
+		p : natural := 8
+	);
+end test_entity;
+
+architecture behaviour of test_entity is
+	type t is array(natural range <>) of std_logic_vector;
+
+	-- all of these work
+	signal s_test1: t(0 to 5-1)(p-1 downto 0);
+	signal s_test2: t(0 to 5-1)(8-1 downto 0);
+	signal s_test3: t(0 to n-1)(p-1 downto 0);
+
+	-- erroring instruction below
+	signal s_test4: t(0 to n-1)(8-1 downto 0);
+begin
+end behaviour;
diff --git a/testsuite/gna/issue756/testsuite.sh b/testsuite/gna/issue756/testsuite.sh
new file mode 100755
index 000000000..6d0877782
--- /dev/null
+++ b/testsuite/gna/issue756/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze test_entity.vhdl
+elab_simulate test_entity
+
+analyze test_entity1.vhdl
+elab_simulate test_entity
+
+clean
+
+echo "Test successful"