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authorTristan Gingold <tgingold@free.fr>2019-05-11 07:21:56 +0200
committerTristan Gingold <tgingold@free.fr>2019-05-11 18:13:37 +0200
commit1daff35f06880b69453a819a0ebc5c6f4adfcf19 (patch)
treed15f6f7ec19d843100322c84597ef52180eacbe8 /testsuite
parent8c03cadc09ad28f0dba75b85e0e6f48667c4e6d6 (diff)
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Add testcase for #772
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/gna/issue772/ent.vhdl38
-rwxr-xr-xtestsuite/gna/issue772/testsuite.sh9
2 files changed, 47 insertions, 0 deletions
diff --git a/testsuite/gna/issue772/ent.vhdl b/testsuite/gna/issue772/ent.vhdl
new file mode 100644
index 000000000..2bcdd4e5a
--- /dev/null
+++ b/testsuite/gna/issue772/ent.vhdl
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity ent is
+end ent;
+
+
+architecture sim of ent is
+
+ signal s_clk : std_logic := '1';
+ signal s_test : std_logic := '0';
+
+begin
+
+ s_clk <= not s_clk after 5 ns;
+ s_test <= '1' after 30 ns,
+ '0' after 40 ns;
+
+ process is
+ begin
+ wait until rising_edge(s_clk);
+ -- This works
+ if s_test'stable(10 ns) then
+ report "s_test stable";
+ else
+ report "s_test changed";
+ end if;
+ end process;
+
+ -- This works
+ -- psl assert always (s_test'stable)@rising_edge(s_clk);
+
+ -- This leads to an compile error
+ -- psl assert always (s_test'stable(10 ns))@rising_edge(s_clk);
+
+end architecture sim;
diff --git a/testsuite/gna/issue772/testsuite.sh b/testsuite/gna/issue772/testsuite.sh
new file mode 100755
index 000000000..0655cfeda
--- /dev/null
+++ b/testsuite/gna/issue772/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze -fpsl ent.vhdl
+
+clean
+
+echo "Test successful"