pyHDL: CLI Update for DOM (#1808)

6 files changed, 78 insertions, 52 deletions

diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl
index a017b9f46..eae346375 100644
--- a/testsuite/pyunit/Current.vhdl
+++ b/testsuite/pyunit/Current.vhdl
@@ -5,12 +5,14 @@ use     ieee.numeric_std.all;
 entity entity_1 is
 	generic (
 		FREQ : real     := 100.0;
-		BITS : positive := 8
+		BITS : positive := 8.5 ns;
+		type Typ
 	);
 	port (
-	  Clock: in  std_logic;
+	  Clock: in  std_logic := 5 ns;
 	  Reset: in  std_logic := '0';
-	  Q:     out std_logic_vector(BITS - 1 downto 0)
+	  D:     inout bit_vector(clock'range);
+	  Q:     out std_logic_vector(BITS'left - 1 downto Re.set)
 	);
 
 	constant fire : boolean := True;
@@ -20,6 +22,7 @@ end entity entity_1;
 
 architecture behav of entity_1 is
 	constant MAX : positive := -25;
+
 	signal rst : std_logic := foo('U');
 	signal vec : bit_vector(pack(3 to 2).signaal'range'value);
 	signal copy : input'subtype;
@@ -74,6 +77,13 @@ architecture behav of entity_1 is
 	attribute att : boolean;
 
 	alias bar is boolean;
+
+	disconnect address_bus : resolved_word after 3 ns;
+	disconnect others : resolved_word after 2 ns;
+
+	default clock is rising_edge(clk);
+	package inner_pack is
+	end package;
 begin
 	process(Clock)
 	begin
@@ -94,18 +104,28 @@ package package_1 is
 
 	use lib.pack.all;
 
-	constant ghdl : float := (3, 5, 0 to 2 => 5, 3 => 4, name => 10); -- 2.3;
-	attribute fixed of ghdl : constant is true;
+  type cell;
+
+	constant ghdl : float := (3, 5, 0 to 2 => 5, 3 => 4, name => 10, others => 10, 2.3);
+	attribute fixed of ghdl, gtkwave [x, y] : constant is true;
 
 	component comp is
 		port (
 			clk : std
 		);
 	end component;
+
+	constant Pointer_1 : List := new List(1 to 1);
+	constant Pointer_2 : List := new List'(1 => 0);
+	signal init : std_logic_vector(abs(mssb_idx(GEN)-GEN'right)-1 downto 0);
+	constant fid : real := +val;
+	constant ceq11 : std_logic := '1' ?= '1';
+	type rt321 is range t3'reverse_range;
+	type rt321 is range t3'reverse_range(1);
 end package;
 
 package body package_1 is
-	constant ghdl : float := (1); -- => 2, 4 => 5, others => 10); -- .5;
+	constant ghdl : float := 1.5;
 
 	type CAPACITY is range 0 to 1E5	units
 		pF;
@@ -115,3 +135,7 @@ package body package_1 is
 		F = 1000 mF;
 	end units;
 end package body;
+
+vunit vu (component_1) {
+
+}
diff --git a/testsuite/pyunit/dom/Expressions.py b/testsuite/pyunit/dom/Expressions.py
index 4de36a2b2..113e541ac 100644
--- a/testsuite/pyunit/dom/Expressions.py
+++ b/testsuite/pyunit/dom/Expressions.py
@@ -87,9 +87,9 @@ class Expressions(TestCase):
         default: Expression = self.parse(filename, constantDeclartion)
 
         # Start checks
-        self.assertTrue(isinstance(default, InverseExpression))
-        self.assertTrue(isinstance(default.Operand, SimpleObjectOrFunctionCallSymbol))
-        self.assertTrue(default.Operand.SymbolName == "true")
+        self.assertIsInstance(default, InverseExpression)
+        self.assertIsInstance(default.Operand, SimpleObjectOrFunctionCallSymbol)
+        self.assertEqual("true", str(default.Operand.SymbolName))
 
     # def test_AbsExpression(self):
     #     filename: Path = self._root / "{className}_{funcName}.vhdl".format(
@@ -103,8 +103,8 @@ class Expressions(TestCase):
     #     default: Expression = self.parse(filename, constantDeclartion)
     #
     #     # Start checks
-    #     self.assertTrue(isinstance(default, AbsoluteExpression))
-    #     self.assertTrue(isinstance(default.Operand, SimpleObjectOrFunctionCallSymbol))
+    #     self.assertIsInstance(default, AbsoluteExpression)
+    #     self.assertIsInstance(default.Operand, SimpleObjectOrFunctionCallSymbol)
     #     self.assertTrue(default.Operand.SymbolName == "-3")
 
     # def test_Aggregare(self):
@@ -130,6 +130,6 @@ class Expressions(TestCase):
     #     package: Package = design.Documents[0].Packages[0]
     #     item: Constant = package.DeclaredItems[0]
     #     default: Expression = item.DefaultExpression
-    #     self.assertTrue(isinstance(default, InverseExpression))
-    #     self.assertTrue(isinstance(default.Operand, SimpleObjectOrFunctionCallSymbol))
+    #     self.assertIsInstance(default, InverseExpression)
+    #     self.assertIsInstance(default.Operand, SimpleObjectOrFunctionCallSymbol)
     #     self.assertTrue(default.Operand.SymbolName == "true")
diff --git a/testsuite/pyunit/dom/Literals.py b/testsuite/pyunit/dom/Literals.py
index a69481ef4..418a1b76d 100644
--- a/testsuite/pyunit/dom/Literals.py
+++ b/testsuite/pyunit/dom/Literals.py
@@ -34,6 +34,10 @@ from pathlib import Path
 from textwrap import dedent
 from unittest import TestCase
 
+from pyVHDLModel.VHDLModel import Expression
+
+from pyGHDL.dom.DesignUnit import Package
+
 from pyGHDL.dom.NonStandard import Design, Document
 from pyGHDL.dom.Object import Constant
 from pyGHDL.dom.Literal import IntegerLiteral
@@ -47,39 +51,38 @@ if __name__ == "__main__":
 
 class Literals(TestCase):
     _root = Path(__file__).resolve().parent.parent
-
-    def test_IntegerLiteral(self):
-        self._filename: Path = self._root / "{className}.vhdl".format(
-            className=self.__class__.__name__
-        )
-
-        sourceCode = dedent(
+    _design = Design()
+    _packageTemplate = dedent(
             """\
             package package_1 is
-              constant c0 : integer := 0;
-              constant c1 : integer := 1;
-              constant c2 : integer := 1024;
-              constant c3 : integer := 1048576;
+              {code}
             end package;
             """
         )
-        expected = (0, 1, 1024, 1048576)
 
-        with self._filename.open(mode="w", encoding="utf-8") as file:
-            file.write(sourceCode)
+    def parse(self, filename: Path, code: str) -> Expression:
+        sourceCode = self._packageTemplate.format(code=code)
+
+        document = Document(filename, sourceCode)
+        self._design.Documents.append(document)
+
+        # Traverse already to default value expression
+        package: Package = document.Packages[0]
+        item: Constant = package.DeclaredItems[0]
+        default: Expression = item.DefaultExpression
+
+        return default
+
+    def test_IntegerLiteral(self):
+        _filename: Path = self._root / "{className}.vhdl".format(
+            className=self.__class__.__name__
+        )
+
+        constantDeclartion = "constant c0 : integer := 0;"
+        expected = (0, 1, 1024, 1048576)
 
-        design = Design()
-        document = Document(self._filename)
-        design.Documents.append(document)
+        # Parse in-memory
+        default: Expression = self.parse(_filename, constantDeclartion)
 
-        self.assertEqual(len(design.Documents[0].Packages), 1)
-        package = design.Documents[0].Packages[0]
-        self.assertTrue(package.Name == "package_1")
-        self.assertEqual(len(package.DeclaredItems), len(expected))
-        for i in range(len(expected)):
-            item: Constant = package.DeclaredItems[i]
-            self.assertTrue(isinstance(item, Constant))
-            self.assertTrue(item.Name == "c{}".format(i))
-            self.assertTrue(str(item.SubType.SymbolName) == "integer")
-            self.assertTrue(isinstance(item.DefaultExpression, IntegerLiteral))
-            self.assertTrue(item.DefaultExpression.Value == expected[i])
+        self.assertIsInstance(default, IntegerLiteral)
+        self.assertEqual(expected[0], default.Value)
diff --git a/testsuite/pyunit/dom/Sanity.py b/testsuite/pyunit/dom/Sanity.py
index b0177f8b3..adf838646 100644
--- a/testsuite/pyunit/dom/Sanity.py
+++ b/testsuite/pyunit/dom/Sanity.py
@@ -49,10 +49,9 @@ _GHDL_ROOT = _TESTSUITE_ROOT.parent
 
 design = Design()
 
-@mark.xfail
 @mark.parametrize("file", [str(f.relative_to(_TESTSUITE_ROOT)) for f in _TESTSUITE_ROOT.glob("sanity/**/*.vhdl")])
 def test_AllVHDLSources(file):
-    check_call([sys_executable, _GHDL_ROOT / "pyGHDL/cli/DOM.py", file], stderr=STDOUT)
+    check_call([sys_executable, _GHDL_ROOT / "pyGHDL/cli/dom.py", "pretty", "-f", file], stderr=STDOUT)
 
 #    document = Document(Path(file))
 #    design.Documents.append(document)
diff --git a/testsuite/pyunit/dom/SimpleEntity.py b/testsuite/pyunit/dom/SimpleEntity.py
index 9ee55508c..68f702410 100644
--- a/testsuite/pyunit/dom/SimpleEntity.py
+++ b/testsuite/pyunit/dom/SimpleEntity.py
@@ -59,20 +59,20 @@ class SimpleEntity(TestCase):
         document = Document(self._filename)
         design.Documents.append(document)
 
-        self.assertTrue(len(design.Documents) == 1)
+        self.assertEqual(1, len(design.Documents))
 
     def test_Entity(self):
         design = Design()
         document = Document(self._filename)
         design.Documents.append(document)
 
-        self.assertEqual(len(design.Documents[0].Entities), 1)
-        self.assertTrue(design.Documents[0].Entities[0].Name == "entity_1")
+        self.assertEqual(1, len(design.Documents[0].Entities))
+        self.assertEqual("entity_1", design.Documents[0].Entities[0].Identifier)
 
     def test_Architecture(self):
         design = Design()
         document = Document(self._filename)
         design.Documents.append(document)
 
-        self.assertEqual(len(design.Documents[0].Architectures), 1)
-        self.assertTrue(design.Documents[0].Architectures[0].Name == "behav")
+        self.assertEqual(1, len(design.Documents[0].Architectures))
+        self.assertEqual("behav", design.Documents[0].Architectures[0].Identifier)
diff --git a/testsuite/pyunit/dom/SimplePackage.py b/testsuite/pyunit/dom/SimplePackage.py
index 399a676b4..9c62db4a1 100644
--- a/testsuite/pyunit/dom/SimplePackage.py
+++ b/testsuite/pyunit/dom/SimplePackage.py
@@ -51,13 +51,13 @@ class SimplePackage(TestCase):
         document = Document(self._filename)
         design.Documents.append(document)
 
-        self.assertEqual(len(design.Documents[0].Packages), 1)
-        self.assertTrue(design.Documents[0].Packages[0].Name == "pack_1")
+        self.assertEqual(1, len(design.Documents[0].Packages))
+        self.assertEqual("pack_1", design.Documents[0].Packages[0].Identifier)
 
     def test_PackageBody(self):
         design = Design()
         document = Document(self._filename)
         design.Documents.append(document)
 
-        self.assertEqual(len(design.Documents[0].PackageBodies), 1)
-        self.assertTrue(design.Documents[0].PackageBodies[0].Name == "pack_1")
+        self.assertEqual(1, len(design.Documents[0].PackageBodies))
+        self.assertEqual("pack_1", design.Documents[0].PackageBodies[0].Identifier)