aboutsummaryrefslogtreecommitdiffstats
path: root/testsuite
diff options
context:
space:
mode:
authorTristan Gingold <tgingold@free.fr>2019-11-23 07:21:06 +0100
committerTristan Gingold <tgingold@free.fr>2019-11-23 07:21:06 +0100
commit1ccba28394a88c1dfa22657bf3cc32b0ba2132c6 (patch)
tree2e50e3e386e687ca5aef0e37ecf702d459a6cdea /testsuite
parentb722d05b25d93f3d2f44b10d7859db2fa7b7ae08 (diff)
downloadghdl-1ccba28394a88c1dfa22657bf3cc32b0ba2132c6.tar.gz
ghdl-1ccba28394a88c1dfa22657bf3cc32b0ba2132c6.tar.bz2
ghdl-1ccba28394a88c1dfa22657bf3cc32b0ba2132c6.zip
Add testcase for #1004.
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/synth/issue1004/firmware.hex3
-rw-r--r--testsuite/synth/issue1004/tb_test2.vhdl34
-rw-r--r--testsuite/synth/issue1004/test.vhdl35
-rw-r--r--testsuite/synth/issue1004/test2.vhdl38
-rwxr-xr-xtestsuite/synth/issue1004/testsuite.sh24
5 files changed, 134 insertions, 0 deletions
diff --git a/testsuite/synth/issue1004/firmware.hex b/testsuite/synth/issue1004/firmware.hex
new file mode 100644
index 000000000..b0402f3cb
--- /dev/null
+++ b/testsuite/synth/issue1004/firmware.hex
@@ -0,0 +1,3 @@
+0102030405060708
+1112131415161718
+2122232425262728
diff --git a/testsuite/synth/issue1004/tb_test2.vhdl b/testsuite/synth/issue1004/tb_test2.vhdl
new file mode 100644
index 000000000..d13513f97
--- /dev/null
+++ b/testsuite/synth/issue1004/tb_test2.vhdl
@@ -0,0 +1,34 @@
+entity tb_test2 is
+end tb_test2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_test2 is
+ signal addr : std_logic_vector(1 downto 0);
+ signal data : std_logic_vector(63 downto 0);
+begin
+ dut: entity work.test2
+ port map (addr, data);
+
+ process
+ begin
+ addr <= b"00";
+ wait for 1 ns;
+ assert data = x"0102030405060708" severity failure;
+
+ addr <= b"01";
+ wait for 1 ns;
+ assert data = x"1112131415161718" severity failure;
+
+ addr <= b"10";
+ wait for 1 ns;
+ assert data = x"2122232425262728" severity failure;
+
+ addr <= b"11";
+ wait for 1 ns;
+ assert data = x"0000000000000000" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/issue1004/test.vhdl b/testsuite/synth/issue1004/test.vhdl
new file mode 100644
index 000000000..bbbbde499
--- /dev/null
+++ b/testsuite/synth/issue1004/test.vhdl
@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+entity test is
+ generic(
+ MEMORY_SIZE : natural := 4096;
+ RAM_INIT_FILE : string := "firmware.hex"
+ );
+end entity test;
+
+architecture behaviour of test is
+ type ram_t is array(0 to (MEMORY_SIZE / 8) - 1) of std_logic_vector(63 downto 0);
+
+ impure function init_ram(name : STRING) return ram_t is
+ file ram_file : text open read_mode is name;
+ variable ram_line : line;
+ variable temp_word : std_logic_vector(63 downto 0);
+ variable temp_ram : ram_t := (others => (others => '0'));
+ begin
+ for i in 0 to (MEMORY_SIZE/8)-1 loop
+ exit when endfile(ram_file);
+ readline(ram_file, ram_line);
+ report "read: " & ram_line.all;
+ hread(ram_line, temp_word);
+ temp_ram(i) := temp_word;
+ end loop;
+
+ return temp_ram;
+ end function;
+
+ signal memory : ram_t := init_ram(RAM_INIT_FILE);
+begin
+end architecture behaviour;
diff --git a/testsuite/synth/issue1004/test2.vhdl b/testsuite/synth/issue1004/test2.vhdl
new file mode 100644
index 000000000..aab224908
--- /dev/null
+++ b/testsuite/synth/issue1004/test2.vhdl
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+entity test2 is
+ generic(
+ MEMORY_SIZE : natural := 32;
+ RAM_INIT_FILE : string := "firmware.hex"
+ );
+ port (addr : std_logic_vector (1 downto 0);
+ data : out std_logic_vector (63 downto 0));
+end entity test2;
+
+architecture behaviour of test2 is
+ type ram_t is array(0 to (MEMORY_SIZE / 8) - 1) of std_logic_vector(63 downto 0);
+
+ impure function init_ram(name : STRING) return ram_t is
+ file ram_file : text open read_mode is name;
+ variable ram_line : line;
+ variable temp_word : std_logic_vector(63 downto 0);
+ variable temp_ram : ram_t := (others => (others => '0'));
+ begin
+ for i in 0 to (MEMORY_SIZE/8)-1 loop
+ exit when endfile(ram_file);
+ readline(ram_file, ram_line);
+ report "read: " & ram_line.all;
+ hread(ram_line, temp_word);
+ temp_ram(i) := temp_word;
+ end loop;
+
+ return temp_ram;
+ end function;
+
+ signal memory : ram_t := init_ram(RAM_INIT_FILE);
+begin
+ data <= memory (to_integer (unsigned (addr)));
+end architecture behaviour;
diff --git a/testsuite/synth/issue1004/testsuite.sh b/testsuite/synth/issue1004/testsuite.sh
new file mode 100755
index 000000000..fa3686042
--- /dev/null
+++ b/testsuite/synth/issue1004/testsuite.sh
@@ -0,0 +1,24 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+for t in test; do
+ synth $t.vhdl -e $t > syn_$t.vhdl
+ analyze syn_$t.vhdl
+done
+
+for t in test2; do
+ analyze $t.vhdl tb_$t.vhdl
+ elab_simulate tb_$t
+ clean
+
+ synth $t.vhdl -e $t > syn_$t.vhdl
+ analyze syn_$t.vhdl tb_$t.vhdl
+ elab_simulate tb_$t --ieee-asserts=disable-at-0
+ clean
+done
+
+clean
+
+echo "Test successful"