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author | Tristan Gingold <tgingold@free.fr> | 2020-05-13 08:26:41 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-05-13 08:26:41 +0200 |
commit | 1c2f3c01628d1ba6f07588d3157a3fac3be23643 (patch) | |
tree | 4685cdea384596dfbca694aba82b40ad49b2da33 /testsuite | |
parent | 53914c09e1f532e0c6fa509634303b3a017dbb97 (diff) | |
download | ghdl-1c2f3c01628d1ba6f07588d3157a3fac3be23643.tar.gz ghdl-1c2f3c01628d1ba6f07588d3157a3fac3be23643.tar.bz2 ghdl-1c2f3c01628d1ba6f07588d3157a3fac3be23643.zip |
testsuite/synth: add a test for #1298
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/synth/issue1298/generics.vhdl | 41 | ||||
-rwxr-xr-x | testsuite/synth/issue1298/testsuite.sh | 15 |
2 files changed, 56 insertions, 0 deletions
diff --git a/testsuite/synth/issue1298/generics.vhdl b/testsuite/synth/issue1298/generics.vhdl new file mode 100644 index 000000000..93e42f5c6 --- /dev/null +++ b/testsuite/synth/issue1298/generics.vhdl @@ -0,0 +1,41 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity Params is + generic ( + BOO : boolean:=FALSE; + INT : integer:=0; + LOG : std_logic:='0'; + VEC : std_logic_vector(7 downto 0):="00000000"; + STR : string:="ABCD"; + REA : real:=0.0 + ); + port ( + boo_o : out std_logic; + int_o : out std_logic_vector(7 downto 0); + log_o : out std_logic; + vec_o : out std_logic_vector(7 downto 0); + str_o : out std_logic; + rea_o : out std_logic + ); +end entity Params; + +architecture RTL of Params is +begin + + assert BOO=True report "The boolean is not True" severity note; + assert INT=255 report "The integer is not 255" severity note; + assert LOG='1' report "The std_logic is not '1'" severity note; + assert VEC="11111111" report "The std_logic_vector is not 11111111" severity note; + assert STR="WXYZ" report "The string is not WXYZ" severity note; +-- assert REA=1.1 report "The real is not 1.1" severity note; + + boo_o <= '1' when BOO else '0'; + int_o <= std_logic_vector(to_unsigned(INT, 8)); + log_o <= LOG; + vec_o <= VEC; + str_o <= '1' when STR="WXYZ" else '0'; + rea_o <= '1' when REA=1.1 else '0'; + +end architecture RTL; diff --git a/testsuite/synth/issue1298/testsuite.sh b/testsuite/synth/issue1298/testsuite.sh new file mode 100755 index 000000000..5cf53b60d --- /dev/null +++ b/testsuite/synth/issue1298/testsuite.sh @@ -0,0 +1,15 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS="-fsynopsys -fexplicit -frelaxed --std=08" + +# synth -gBOO=true -gINT=255 -gLOG=\'1\' -gSTR="WXYZ" generics.vhdl -e Params + +synth -gBOO=true -gINT=255 -gLOG=\'1\' -gSTR="WXYZ" -gVEC="11111111" --out=none generics.vhdl -e Params + +synth_failure -gBOO=true -gINT=255 -gLOG=\'1\' -gSTR="WXYZ" -gVEC=\"11111111\" --out=none generics.vhdl -e Params + +synth_failure -gBOO=true -gINT=255 -gLOG=\'1\' -gSTR="WXYZ" -gREA=1.1 generics.vhdl -e Params + +echo "Test successful" |