testsuite/synth: add simple01

3 files changed, 64 insertions, 0 deletions

diff --git a/testsuite/synth/simple01/simple01.vhdl b/testsuite/synth/simple01/simple01.vhdl
new file mode 100644
index 000000000..45c96f1d4
--- /dev/null
+++ b/testsuite/synth/simple01/simple01.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity simple01 is
+  port (a, b, c : in std_logic;
+        z : out std_logic);
+end simple01;
+
+architecture behav of simple01 is
+begin
+  process(A, B, C)
+    variable temp : std_logic;
+  begin
+    temp := A and B;
+    Z <= temp or C;
+  end process;
+end behav;
diff --git a/testsuite/synth/simple01/tb_simple01.vhdl b/testsuite/synth/simple01/tb_simple01.vhdl
new file mode 100644
index 000000000..634ffa396
--- /dev/null
+++ b/testsuite/synth/simple01/tb_simple01.vhdl
@@ -0,0 +1,31 @@
+entity tb_simple01 is
+end tb_simple01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_simple01 is
+  signal a : std_logic;
+  signal b : std_logic;
+  signal c : std_logic;
+  signal z : std_logic;
+begin
+  dut: entity work.simple01
+    port map (a, b, c, z);
+
+  process
+    constant av : std_logic_vector := b"1101";
+    constant bv : std_logic_vector := b"0111";
+    constant cv : std_logic_vector := b"0011";
+    constant zv : std_logic_vector := b"0111";
+  begin
+    for i in av'range loop
+      a <= av (i);
+      b <= bv (i);
+      c <= cv (i);
+      wait for 1 ns;
+      assert z = zv(i) severity failure;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/simple01/testsuite.sh b/testsuite/synth/simple01/testsuite.sh
new file mode 100755
index 000000000..3f7fd19d9
--- /dev/null
+++ b/testsuite/synth/simple01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in simple01; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
+
+echo "Test successful"