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author | Tristan Gingold <tgingold@free.fr> | 2019-12-30 16:22:28 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-12-30 16:22:28 +0100 |
commit | 2bb69da764f47506620809602ed08ce1bf5facc4 (patch) | |
tree | cb9d268691c61bc239b99c70e27ca63ea46471cd /testsuite/vests/vhdl-ams | |
parent | 15ae95c16ee4bf00432e43afd693ab4aa5ada138 (diff) | |
download | ghdl-2bb69da764f47506620809602ed08ce1bf5facc4.tar.gz ghdl-2bb69da764f47506620809602ed08ce1bf5facc4.tar.bz2 ghdl-2bb69da764f47506620809602ed08ce1bf5facc4.zip |
testsuite/vests/vhdl-ams/ashenden: fix some tests.
Diffstat (limited to 'testsuite/vests/vhdl-ams')
-rw-r--r-- | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/stop_r.vhd | 8 | ||||
-rw-r--r-- | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_10a.vhd | 2 |
2 files changed, 4 insertions, 6 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/stop_r.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/stop_r.vhd index 4a6c037ca..824ef7bc4 100644 --- a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/stop_r.vhd +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/stop_r.vhd @@ -31,19 +31,19 @@ end entity stop_r; architecture ideal of stop_r is - quantity velocity : velocity; + quantity qvelocity : velocity; quantity ang across trq through ang1 to ang2; begin - velocity == ang'dot; + qvelocity == ang'dot; if ang > ang_max use -- Hit upper stop, generate opposing torque - trq == k_stop * (ang - ang_max) + (damp_stop * velocity); + trq == k_stop * (ang - ang_max) + (damp_stop * qvelocity); elsif ang > ang_min use -- Between stops, no opposing torque trq == 0.0; else -- Hit lower stop, generate opposing torque - trq == k_stop * (ang - ang_min) + (damp_stop * velocity); + trq == k_stop * (ang - ang_min) + (damp_stop * qvelocity); end use; break on ang'above(ang_min), ang'above(ang_max); diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_10a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_10a.vhd index a6c3191c0..8888a7e55 100644 --- a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_10a.vhd +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_10a.vhd @@ -212,6 +212,4 @@ begin end block block_9; - -begin end architecture test; |