diff options
author | Tristan Gingold <tgingold@free.fr> | 2013-12-20 04:48:54 +0100 |
---|---|---|
committer | Tristan Gingold <tgingold@free.fr> | 2013-12-20 04:48:54 +0100 |
commit | 6c3f709174e8e4d5411f851cedb7d84c38d3b04a (patch) | |
tree | bd12c79c71a2ee65899a9ade9919ec2045addef8 /testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd | |
parent | bd4aff0f670351c0652cf24e9b04361dc0e3a01c (diff) | |
download | ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.tar.gz ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.tar.bz2 ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.zip |
Import vests testsuite
Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd')
-rw-r--r-- | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd new file mode 100644 index 000000000..479c3af75 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; + +entity and2 is + port ( a, b : in std_ulogic; y : out std_ulogic ); +end entity and2; + +-------------------------------------------------- + +architecture detailed_delay of and2 is + + signal result : std_ulogic; + +begin + + gate : process (a, b) is + begin + result <= a and b; + end process gate; + + delay : process (result) is + begin + if result = '1' then + y <= reject 400 ps inertial '1' after 1.5 ns; + elsif result = '0' then + y <= reject 300 ps inertial '0' after 1.2 ns; + else + y <= reject 300 ps inertial 'X' after 500 ps; + end if; + end process delay; + +end architecture detailed_delay; |