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author | Tristan Gingold <tgingold@free.fr> | 2013-12-20 04:48:54 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2013-12-20 04:48:54 +0100 |
commit | 6c3f709174e8e4d5411f851cedb7d84c38d3b04a (patch) | |
tree | bd12c79c71a2ee65899a9ade9919ec2045addef8 /testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-assign.vhdl | |
parent | bd4aff0f670351c0652cf24e9b04361dc0e3a01c (diff) | |
download | ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.tar.gz ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.tar.bz2 ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.zip |
Import vests testsuite
Diffstat (limited to 'testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-assign.vhdl')
-rw-r--r-- | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-assign.vhdl | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-assign.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-assign.vhdl new file mode 100644 index 000000000..3efa37b6e --- /dev/null +++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-assign.vhdl @@ -0,0 +1,23 @@ +entity test_bench is +end test_bench; + +architecture only of test_bench is + signal sig : integer := 0; +begin -- only + p: process + begin -- process p + sig <= 1; + wait for 1 fs; + assert sig = 1 report "TEST FAILED" severity FAILURE; + report "TEST PASSED" severity NOTE; + wait; + end process p; + + r: process (sig) + begin -- process r + if sig'event then + report "Event on sig, new value = " & integer'image( sig ); + end if; + end process r; + +end only; |