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author | Tristan Gingold <tgingold@free.fr> | 2013-12-20 04:48:54 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2013-12-20 04:48:54 +0100 |
commit | 6c3f709174e8e4d5411f851cedb7d84c38d3b04a (patch) | |
tree | bd12c79c71a2ee65899a9ade9919ec2045addef8 /testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_05.vhd | |
parent | bd4aff0f670351c0652cf24e9b04361dc0e3a01c (diff) | |
download | ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.tar.gz ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.tar.bz2 ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.zip |
Import vests testsuite
Diffstat (limited to 'testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_05.vhd')
-rw-r--r-- | testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_05.vhd | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_05.vhd new file mode 100644 index 000000000..4303bd94d --- /dev/null +++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_05.vhd @@ -0,0 +1,88 @@ + +-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: ch_16_ch_16_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $ +-- $Revision: 1.1.1.1 $ +-- +-- --------------------------------------------------------------------- + +entity ch_16_05 is + +end entity ch_16_05; + + +---------------------------------------------------------------- + + +architecture test of ch_16_05 is + + subtype word is bit_vector(0 to 31); + type word_array is array (integer range <>) of word; + + function resolve_words ( words : word_array ) return word is + begin + if words'length > 0 then + return words(words'left); + else + return X"00000000"; + end if; + end function resolve_words; + + subtype resolved_word is resolve_words word; + + -- code from book: + + signal source_bus_1, source_bus_2 : resolved_word bus; + signal address_bus : resolved_word bus; + + disconnect all : resolved_word after 2 ns; + + -- end of code from book + + signal s : word; + signal g : boolean; + +begin + + + b : block (g) is + begin + source_bus_1 <= guarded s after 4 ns; + source_bus_2 <= guarded s after 4 ns; + address_bus <= guarded s after 4 ns; + end block b; + + stimulus : process is + begin + s <= X"DDDDDDDD"; + wait for 10 ns; + g <= true; + wait for 10 ns; + s <= X"AAAAAAAA"; + wait for 10 ns; + g <= false; + wait for 10 ns; + s <= X"11111111"; + + wait; + end process stimulus; + +end architecture test; |