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author | Tristan Gingold <tgingold@free.fr> | 2013-12-20 04:48:54 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2013-12-20 04:48:54 +0100 |
commit | 6c3f709174e8e4d5411f851cedb7d84c38d3b04a (patch) | |
tree | bd12c79c71a2ee65899a9ade9919ec2045addef8 /testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_18.vhd | |
parent | bd4aff0f670351c0652cf24e9b04361dc0e3a01c (diff) | |
download | ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.tar.gz ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.tar.bz2 ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.zip |
Import vests testsuite
Diffstat (limited to 'testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_18.vhd')
-rw-r--r-- | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_18.vhd | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_18.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_18.vhd new file mode 100644 index 000000000..e7ba617f7 --- /dev/null +++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_18.vhd @@ -0,0 +1,76 @@ + +-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: ch_13_fg_13_18.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $ +-- $Revision: 1.3 $ +-- +-- --------------------------------------------------------------------- + +entity XYZ3000_cpu is + port ( clock : in bit; addr_data : inout bit_vector(31 downto 0); + other_port : in bit := '0' ); +end entity XYZ3000_cpu; + +architecture full_function of XYZ3000_cpu is +begin +end architecture full_function; + + +entity memory_array is + port ( addr : in bit_vector(25 downto 0); other_port : in bit := '0' ); +end entity memory_array; + + +architecture behavioral of memory_array is +begin +end architecture behavioral; + +-- code from book + +library chips; + +configuration intermediate of single_board_computer is + + for structural + + for cpu : processor + use entity chips.XYZ3000_cpu(full_function) + port map ( clock => clk, addr_data => a_d, -- . . . ); + -- not in book + other_port => open ); + -- end not in book + end for; + + for main_memory : memory + use entity work.memory_array(behavioral); + end for; + + for all : serial_interface + use open; + end for; + + -- . . . + + end for; + +end configuration intermediate; + +-- end code from book |