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| author | Tristan Gingold <tgingold@free.fr> | 2022-06-27 19:35:45 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-06-27 19:37:33 +0200 |
| commit | ffdec03a786b19cb9967034bb5cd1ca8b7034c1f (patch) | |
| tree | 23e65622344ae355d308587406e502ffe967a7b6 /testsuite/synth | |
| parent | a036958a9adc31011729aab02af9eec48f80bc8a (diff) | |
| download | ghdl-ffdec03a786b19cb9967034bb5cd1ca8b7034c1f.tar.gz ghdl-ffdec03a786b19cb9967034bb5cd1ca8b7034c1f.tar.bz2 ghdl-ffdec03a786b19cb9967034bb5cd1ca8b7034c1f.zip | |
synth/netlists-disp_verilog: skip null input port. Fix #2113
Diffstat (limited to 'testsuite/synth')
0 files changed, 0 insertions, 0 deletions