synth: Support alias declarations in vunit

3 files changed, 32 insertions, 0 deletions

diff --git a/testsuite/synth/psl02/assert2.vhdl b/testsuite/synth/psl02/assert2.vhdl
index 0286470c8..9b5c351f7 100644
--- a/testsuite/synth/psl02/assert2.vhdl
+++ b/testsuite/synth/psl02/assert2.vhdl
@@ -9,6 +9,10 @@ end assert2;
 
 architecture behav of assert2 is
  signal val : unsigned (3 downto 0);
+ function incr (a : integer) return integer is
+ begin
+   return a + 1;
+ end function incr;
 begin
  process(clk)
  begin
diff --git a/testsuite/synth/psl02/testsuite.sh b/testsuite/synth/psl02/testsuite.sh
index 76b8c58eb..a45a0e0ff 100755
--- a/testsuite/synth/psl02/testsuite.sh
+++ b/testsuite/synth/psl02/testsuite.sh
@@ -27,4 +27,9 @@ analyze syn_assert23.vhdl
 
 clean
 
+synth assert2.vhdl verif5.vhdl -e assert2 > syn_assert25.vhdl
+analyze syn_assert25.vhdl
+
+clean
+
 echo "Test successful"
diff --git a/testsuite/synth/psl02/verif5.vhdl b/testsuite/synth/psl02/verif5.vhdl
new file mode 100644
index 000000000..c4d8c02e0
--- /dev/null
+++ b/testsuite/synth/psl02/verif5.vhdl
@@ -0,0 +1,23 @@
+vunit verif5 (assert2(behav))
+{
+  signal cnti : natural;
+
+  -- Aliases to objects
+  alias cnti_a is cnti;
+  alias clk_a is clk;
+  alias rst_a is rst;
+  alias cnt_a is cnt;
+
+  -- Alias to non-object
+  alias incr_a is incr[integer return integer];
+
+  cnti_a <= to_integer(cnt);
+
+  default clock is rising_edge(clk_a);
+
+  assert always cnt_a /= 5 abort rst_a;
+  assert always rst_a = rst;
+  assert always cnt_a = cnt;
+  assert always cnti_a = cnt;
+  assert always cnti_a = incr_a(prev(cnti_a));
+}