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author | Tristan Gingold <tgingold@free.fr> | 2021-02-12 18:12:37 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-02-12 18:12:56 +0100 |
commit | e4f4501e1bf7a59d9d8b453746d55715321635e6 (patch) | |
tree | 7655b54275ba675d3ddd438fc1b5d208b7a98721 /testsuite/synth | |
parent | 7cf780c73be8429720195ddeaeb3682b106f4c38 (diff) | |
download | ghdl-e4f4501e1bf7a59d9d8b453746d55715321635e6.tar.gz ghdl-e4f4501e1bf7a59d9d8b453746d55715321635e6.tar.bz2 ghdl-e4f4501e1bf7a59d9d8b453746d55715321635e6.zip |
testsuite/synth: add a test for #1645
Diffstat (limited to 'testsuite/synth')
-rw-r--r-- | testsuite/synth/issue1645/ent.vhdl | 41 | ||||
-rw-r--r-- | testsuite/synth/issue1645/tb_ent.vhdl | 37 | ||||
-rwxr-xr-x | testsuite/synth/issue1645/testsuite.sh | 7 |
3 files changed, 85 insertions, 0 deletions
diff --git a/testsuite/synth/issue1645/ent.vhdl b/testsuite/synth/issue1645/ent.vhdl new file mode 100644 index 000000000..05dfc5da4 --- /dev/null +++ b/testsuite/synth/issue1645/ent.vhdl @@ -0,0 +1,41 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ent is + generic (size : natural := 4); + port ( + clk : in std_logic; + r : out std_logic + ); +end entity ent; + +architecture rtl of ent is + + type ram_type is array (0 to size-1) of std_logic_vector(7 downto 0); + subtype index_type is natural range ram_type'range; -- This declaration leads to incorrect sign-extension +-- subtype index_type is natural range 0 to size-1; -- This declaration leads to correct unsigned comparison. + signal a : index_type := 0; + +begin + + process (clk) + begin + if rising_edge(clk) then + if a = index_type'high then + a <= index_type'low; + else + a <= a + 1; + end if; + end if; + end process; + + process (a) + begin + if a < 3 then + r <= '1'; + else + r <= '0'; + end if; + end process; +end architecture rtl; diff --git a/testsuite/synth/issue1645/tb_ent.vhdl b/testsuite/synth/issue1645/tb_ent.vhdl new file mode 100644 index 000000000..bed9fcfc3 --- /dev/null +++ b/testsuite/synth/issue1645/tb_ent.vhdl @@ -0,0 +1,37 @@ +entity tb_ent is +end tb_ent; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_ent is + signal clk : std_logic; + signal r : std_logic; +begin + dut: entity work.ent + port map ( + clk => clk, + r => r); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + wait for 1 ns; + assert r = '1' severity failure; + pulse; + assert r = '1' severity failure; + pulse; + assert r = '1' severity failure; + pulse; + assert r = '0' severity failure; + pulse; + assert r = '1' severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/issue1645/testsuite.sh b/testsuite/synth/issue1645/testsuite.sh new file mode 100755 index 000000000..5c1da263d --- /dev/null +++ b/testsuite/synth/issue1645/testsuite.sh @@ -0,0 +1,7 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_tb ent + +echo "Test successful" |