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author | Tristan Gingold <tgingold@free.fr> | 2022-06-11 15:00:45 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-06-11 15:02:50 +0200 |
commit | 94b4a64e50d20948176b3f912e65878fb5945231 (patch) | |
tree | 7a514c1733f2207b9e730d08cf9ef234377734da /testsuite/synth | |
parent | 414610b92c49370d74ecb70edd98b6c4a9e29d77 (diff) | |
download | ghdl-94b4a64e50d20948176b3f912e65878fb5945231.tar.gz ghdl-94b4a64e50d20948176b3f912e65878fb5945231.tar.bz2 ghdl-94b4a64e50d20948176b3f912e65878fb5945231.zip |
testsuite/synth: add a test for #2086
Diffstat (limited to 'testsuite/synth')
-rw-r--r-- | testsuite/synth/issue2086/repro4.vhdl | 28 | ||||
-rwxr-xr-x | testsuite/synth/issue2086/testsuite.sh | 7 |
2 files changed, 35 insertions, 0 deletions
diff --git a/testsuite/synth/issue2086/repro4.vhdl b/testsuite/synth/issue2086/repro4.vhdl new file mode 100644 index 000000000..ef4da6a42 --- /dev/null +++ b/testsuite/synth/issue2086/repro4.vhdl @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity repro4 is + port ( + rst : std_logic; + clk : std_logic; + de : std_logic; + vs_o : out std_logic); +end; + +architecture synth of repro4 is + type mem_t is array(0 to 15) of std_logic; + + signal mem : mem_t; + signal addr : integer range mem_t'range; +begin + process(rst, clk) + begin + if rst = '1' then + addr <= 0; + elsif rising_edge(clk) then + vs_o <= mem(addr); + mem(addr) <= de; + addr <= addr+1; + end if; + end process; +end; diff --git a/testsuite/synth/issue2086/testsuite.sh b/testsuite/synth/issue2086/testsuite.sh new file mode 100755 index 000000000..258102547 --- /dev/null +++ b/testsuite/synth/issue2086/testsuite.sh @@ -0,0 +1,7 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_only repro4 + +echo "Test successful" |