testsuite/synth: add testcase for #960

5 files changed, 133 insertions, 0 deletions

diff --git a/testsuite/synth/issue960/ent.vhdl b/testsuite/synth/issue960/ent.vhdl
new file mode 100644
index 000000000..41873645d
--- /dev/null
+++ b/testsuite/synth/issue960/ent.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+    port (
+        clk : in std_logic
+    );
+end;
+
+architecture a of ent is
+    procedure inv(signal s : inout std_logic) is
+    begin
+        s <= not s;
+    end procedure;
+
+    signal test : std_logic;
+begin
+    process(clk)
+    begin
+        if rising_edge(clk) then
+            inv(test);
+        end if;
+    end process;
+end;
diff --git a/testsuite/synth/issue960/ent2.vhdl b/testsuite/synth/issue960/ent2.vhdl
new file mode 100644
index 000000000..0b270909a
--- /dev/null
+++ b/testsuite/synth/issue960/ent2.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent2 is
+    port (
+      clk : in std_logic;
+      o : out std_logic
+    );
+end;
+
+architecture a of ent2 is
+    procedure inv(signal s : inout std_logic) is
+    begin
+        s <= not s;
+    end procedure;
+
+    signal test : std_logic := '0';
+begin
+    process(clk)
+    begin
+      if rising_edge(clk) then
+        inv(test);
+      end if;
+    end process;
+    o <= test;
+end;
diff --git a/testsuite/synth/issue960/ent3.vhdl b/testsuite/synth/issue960/ent3.vhdl
new file mode 100644
index 000000000..8db4537ea
--- /dev/null
+++ b/testsuite/synth/issue960/ent3.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+    port (
+      clk : in std_logic;
+      o : out std_logic
+    );
+end;
+
+architecture a of ent is
+  function inv(s : std_logic) return std_logic is
+  begin
+    return not s;
+  end inv;
+
+    signal test : std_logic;
+begin
+    process(clk)
+    begin
+      if rising_edge(clk) then
+        test <= inv(test);
+      end if;
+    end process;
+    o <= test;
+end;
diff --git a/testsuite/synth/issue960/tb_ent2.vhdl b/testsuite/synth/issue960/tb_ent2.vhdl
new file mode 100644
index 000000000..77ba52a31
--- /dev/null
+++ b/testsuite/synth/issue960/tb_ent2.vhdl
@@ -0,0 +1,39 @@
+entity tb_ent2 is
+end tb_ent2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ent2 is
+  signal clk : std_logic;
+  signal dout : std_logic;
+begin
+  dut: entity work.ent2
+    port map (
+      o => dout,
+      clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    wait for 1 ns;
+    assert dout = '0' severity failure;
+
+    pulse;
+    assert dout = '1' severity failure;
+
+    pulse;
+    assert dout = '0' severity failure;
+
+    pulse;
+    assert dout = '1' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue960/testsuite.sh b/testsuite/synth/issue960/testsuite.sh
new file mode 100755
index 000000000..eef613a45
--- /dev/null
+++ b/testsuite/synth/issue960/testsuite.sh
@@ -0,0 +1,18 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in ent2; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+synth ent.vhdl -e > syn_ent.vhdl
+
+echo "Test successful"