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author | Tristan Gingold <tgingold@free.fr> | 2019-10-24 20:10:18 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-24 20:10:18 +0200 |
commit | 7cbc90ca65509c5ebbb39c4c06b68414053f00ec (patch) | |
tree | 605c4dac9730dbb1be95fe53a45075216d538ae4 /testsuite/synth | |
parent | 32c88bc9f4eaf455290af582b6494c8b2e2f8a58 (diff) | |
download | ghdl-7cbc90ca65509c5ebbb39c4c06b68414053f00ec.tar.gz ghdl-7cbc90ca65509c5ebbb39c4c06b68414053f00ec.tar.bz2 ghdl-7cbc90ca65509c5ebbb39c4c06b68414053f00ec.zip |
Add testcase for previous commit.
Diffstat (limited to 'testsuite/synth')
-rwxr-xr-x | testsuite/synth/psl02/testsuite.sh | 5 | ||||
-rw-r--r-- | testsuite/synth/psl02/verif4.vhdl | 10 |
2 files changed, 15 insertions, 0 deletions
diff --git a/testsuite/synth/psl02/testsuite.sh b/testsuite/synth/psl02/testsuite.sh index 0b16872c1..76b8c58eb 100755 --- a/testsuite/synth/psl02/testsuite.sh +++ b/testsuite/synth/psl02/testsuite.sh @@ -22,4 +22,9 @@ analyze syn_assert23.vhdl clean +synth assert2.vhdl verif4.vhdl -e assert2 > syn_assert24.vhdl +analyze syn_assert23.vhdl + +clean + echo "Test successful" diff --git a/testsuite/synth/psl02/verif4.vhdl b/testsuite/synth/psl02/verif4.vhdl new file mode 100644 index 000000000..a8e4fff5a --- /dev/null +++ b/testsuite/synth/psl02/verif4.vhdl @@ -0,0 +1,10 @@ +vunit verif4 (assert2(behav)) +{ + default clock is rising_edge(clk); + function check_val (v : unsigned) return boolean is + begin + return v < 10; + end check_val; + assume always check_val (val); + assert always val /= 5 abort rst; +} |