testsuite/synth: add a test for #1912

2 files changed, 82 insertions, 0 deletions

diff --git a/testsuite/synth/issue1912/popcount.vhdl b/testsuite/synth/issue1912/popcount.vhdl
new file mode 100644
index 000000000..174b50f51
--- /dev/null
+++ b/testsuite/synth/issue1912/popcount.vhdl
@@ -0,0 +1,75 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+
+entity popcount is
+	generic (
+		SIZE  : natural := 32
+	);
+	port (
+		-- Input data
+		data : in std_logic_vector(SIZE-1 downto 0);
+		-- Results
+		num  : out std_logic
+	);
+end entity;
+
+architecture synth of popcount is
+
+	-- Component declaration of itself, for recursive instantiation
+
+	component popcount is
+		generic (
+			SIZE  : natural := 32
+		);
+		port (
+			-- Input data
+			data : in std_logic_vector(SIZE-1 downto 0);
+			-- Results
+			num  : out std_logic
+		);
+	end component;
+
+begin
+
+	n5 : if SIZE <= 5 generate
+
+		num <= '1';
+
+	end generate;
+
+	more : if SIZE >= 6 generate
+
+		signal num_1 : std_logic;
+		signal num_2 : std_logic;
+
+		constant SIZE_LOWER : natural := 4 * (SIZE / 5);
+
+	begin
+
+		inst1 : popcount
+			generic map (
+				SIZE  => SIZE_LOWER
+			)
+			port map (
+				data => data(SIZE_LOWER-1 downto 0),
+				num  => num_1
+			);
+
+		inst2 : popcount
+			generic map (
+				SIZE  => SIZE - SIZE_LOWER
+			)
+			port map (
+				data => data(SIZE-1 downto SIZE_LOWER),
+				num  => num_2
+			);
+
+		num <= num_1 or num_2;
+
+	end generate;
+
+end architecture;
diff --git a/testsuite/synth/issue1912/testsuite.sh b/testsuite/synth/issue1912/testsuite.sh
new file mode 100755
index 000000000..e41b66aee
--- /dev/null
+++ b/testsuite/synth/issue1912/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth popcount.vhdl -e popcount > syn_popcount.vhdl
+
+echo "Test successful"