testsuite/synth: add tests for rol/ror. For #1909

5 files changed, 85 insertions, 1 deletions

diff --git a/testsuite/synth/oper02/srot01.vhdl b/testsuite/synth/oper02/srot01.vhdl
new file mode 100644
index 000000000..0dc382871
--- /dev/null
+++ b/testsuite/synth/oper02/srot01.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+
+entity Srot01 is
+  port(
+    v    : in  signed(7 downto 0);
+    ro   : out signed(7 downto 0);
+    lo   : out signed(7 downto 0)
+  );
+end Srot01;
+
+architecture rtl of Srot01 is
+begin
+  ro <= v ror 1;
+  lo <= v rol 1;
+end rtl;
diff --git a/testsuite/synth/oper02/tb_srot01.vhdl b/testsuite/synth/oper02/tb_srot01.vhdl
new file mode 100644
index 000000000..66e8e3292
--- /dev/null
+++ b/testsuite/synth/oper02/tb_srot01.vhdl
@@ -0,0 +1,25 @@
+entity tb_srot01 is
+end tb_srot01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_srot01 is
+  signal v    : signed(7 downto 0);
+  signal ro   : signed(7 downto 0);
+  signal lo   : signed(7 downto 0);
+begin
+  dut: entity work.srot01
+    port map (v, ro, lo);
+
+  process
+  begin
+    v <= x"14";
+    wait for 1 ns;
+    assert ro = x"0a" severity failure;
+    assert lo = x"28" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/oper02/tb_urot01.vhdl b/testsuite/synth/oper02/tb_urot01.vhdl
new file mode 100644
index 000000000..2875bbe96
--- /dev/null
+++ b/testsuite/synth/oper02/tb_urot01.vhdl
@@ -0,0 +1,25 @@
+entity tb_urot01 is
+end tb_urot01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_urot01 is
+  signal v    : unsigned(7 downto 0);
+  signal ro   : unsigned(7 downto 0);
+  signal lo   : unsigned(7 downto 0);
+begin
+  dut: entity work.urot01
+    port map (v, ro, lo);
+
+  process
+  begin
+    v <= x"14";
+    wait for 1 ns;
+    assert ro = x"0a" severity failure;
+    assert lo = x"28" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/oper02/testsuite.sh b/testsuite/synth/oper02/testsuite.sh
index 6fb2d7ca4..889f20b54 100755
--- a/testsuite/synth/oper02/testsuite.sh
+++ b/testsuite/synth/oper02/testsuite.sh
@@ -3,7 +3,7 @@
 . ../../testenv.sh
 
 GHDL_STD_FLAGS=--std=08
-for t in min01 max01 uns02; do
+for t in min01 max01 uns02 urot01 srot01; do
     synth_tb $t
 done
 
diff --git a/testsuite/synth/oper02/urot01.vhdl b/testsuite/synth/oper02/urot01.vhdl
new file mode 100644
index 000000000..e798e09dd
--- /dev/null
+++ b/testsuite/synth/oper02/urot01.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+
+entity Urot01 is
+  port(
+    v    : in unsigned(7 downto 0);
+    ro   : out unsigned(7 downto 0);
+    lo   : out unsigned(7 downto 0)
+  );
+end Urot01;
+
+architecture rtl of Urot01 is
+begin
+  ro <= v ror 1;
+  lo <= v rol 1;
+end rtl;