testsuite/synth/dff01: add testbenches.

14 files changed, 453 insertions, 14 deletions

diff --git a/testsuite/synth/dff01/dff04.vhdl b/testsuite/synth/dff01/dff04.vhdl
index 9e7e60478..29ea5fee0 100644
--- a/testsuite/synth/dff01/dff04.vhdl
+++ b/testsuite/synth/dff01/dff04.vhdl
@@ -11,7 +11,7 @@ end dff04;
 architecture behav of dff04 is
   signal q : std_logic_vector(7 downto 0);
 begin
-  process (clk) is
+  process (clk, q) is
   begin
     if rising_edge (clk) then
       q <= d;
diff --git a/testsuite/synth/dff01/dff05.vhdl b/testsuite/synth/dff01/dff05.vhdl
index cd109a439..182dd737d 100644
--- a/testsuite/synth/dff01/dff05.vhdl
+++ b/testsuite/synth/dff01/dff05.vhdl
@@ -11,7 +11,7 @@ end dff05;
 
 architecture behav of dff05 is
 begin
-  process (clk) is
+  process (clk, rst) is
   begin
     if rst = '1' then
       q <= x"00";
diff --git a/testsuite/synth/dff01/dff10.vhdl b/testsuite/synth/dff01/dff10.vhdl
index 86af44865..5a111c7b5 100644
--- a/testsuite/synth/dff01/dff10.vhdl
+++ b/testsuite/synth/dff01/dff10.vhdl
@@ -11,7 +11,7 @@ end dff10;
 
 architecture behav of dff10 is
 begin
-  process (clk) is
+  process (clk, rst) is
     constant rval : std_logic_vector(7 downto 0) := x"55";
   begin
     if rst = '1' then
diff --git a/testsuite/synth/dff01/tb_dff01.vhdl b/testsuite/synth/dff01/tb_dff01.vhdl
new file mode 100644
index 000000000..7008a8b95
--- /dev/null
+++ b/testsuite/synth/dff01/tb_dff01.vhdl
@@ -0,0 +1,40 @@
+entity tb_dff01 is
+end tb_dff01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff01 is
+  signal clk : std_logic;
+  signal din : std_logic;
+  signal dout : std_logic;
+begin
+  dut: entity work.dff01
+    port map (
+      q => dout,
+      d => din,
+      clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    din <= '0';
+    pulse;
+    assert dout = '0' severity failure;
+    din <= '1';
+    pulse;
+    assert dout = '1' severity failure;
+    pulse;
+    assert dout = '1' severity failure;
+    din <= '0';
+    pulse;
+    assert dout = '0' severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/tb_dff02.vhdl b/testsuite/synth/dff01/tb_dff02.vhdl
new file mode 100644
index 000000000..44cf1fc74
--- /dev/null
+++ b/testsuite/synth/dff01/tb_dff02.vhdl
@@ -0,0 +1,47 @@
+entity tb_dff02 is
+end tb_dff02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff02 is
+  signal clk : std_logic;
+  signal rstn : std_logic;
+  signal din : std_logic;
+  signal dout : std_logic;
+begin
+  dut: entity work.dff02
+    port map (
+      q => dout,
+      d => din,
+      clk => clk,
+      rstn => rstn);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rstn <= '0';
+    wait for 1 ns;
+    assert dout = '0' severity failure;
+    rstn <= '1';
+    din <= '1';
+    pulse;
+    assert dout = '1' severity failure;
+    din <= '0';
+    pulse;
+    assert dout = '0' severity failure;
+    din <= '1';
+    pulse;
+    assert dout = '1' severity failure;
+    rstn <= '0';
+    wait for 1 ns;
+    assert dout = '0' severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/tb_dff03.vhdl b/testsuite/synth/dff01/tb_dff03.vhdl
new file mode 100644
index 000000000..97d60d684
--- /dev/null
+++ b/testsuite/synth/dff01/tb_dff03.vhdl
@@ -0,0 +1,40 @@
+entity tb_dff03 is
+end tb_dff03;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff03 is
+  signal clk : std_logic;
+  signal din : std_logic_vector (7 downto 0);
+  signal dout : std_logic_vector (7 downto 0);
+begin
+  dut: entity work.dff03
+    port map (
+      q => dout,
+      d => din,
+      clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    din <= x"00";
+    pulse;
+    assert dout = x"00" severity failure;
+    din <= x"ab";
+    pulse;
+    assert dout = x"ab" severity failure;
+    pulse;
+    assert dout = x"ab" severity failure;
+    din <= x"12";
+    pulse;
+    assert dout = x"12" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/tb_dff04.vhdl b/testsuite/synth/dff01/tb_dff04.vhdl
new file mode 100644
index 000000000..1d3b3146f
--- /dev/null
+++ b/testsuite/synth/dff01/tb_dff04.vhdl
@@ -0,0 +1,40 @@
+entity tb_dff04 is
+end tb_dff04;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff04 is
+  signal clk : std_logic;
+  signal din : std_logic_vector (7 downto 0);
+  signal dout : std_logic_vector (7 downto 0);
+begin
+  dut: entity work.dff04
+    port map (
+      r => dout,
+      d => din,
+      clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    din <= x"00";
+    pulse;
+    assert dout = x"01" severity failure;
+    din <= x"ab";
+    pulse;
+    assert dout = x"ac" severity failure;
+    pulse;
+    assert dout = x"ac" severity failure;
+    din <= x"12";
+    pulse;
+    assert dout = x"13" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/tb_dff05.vhdl b/testsuite/synth/dff01/tb_dff05.vhdl
new file mode 100644
index 000000000..48651fa1b
--- /dev/null
+++ b/testsuite/synth/dff01/tb_dff05.vhdl
@@ -0,0 +1,54 @@
+entity tb_dff05 is
+end tb_dff05;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff05 is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal din : std_logic_vector (7 downto 0);
+  signal dout : std_logic_vector (7 downto 0);
+  signal en : std_logic;
+begin
+  dut: entity work.dff05
+    port map (
+      q => dout,
+      d => din,
+      clk => clk,
+      rst => rst,
+      en => en);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    en <= '1';
+    wait for 1 ns;
+    assert dout = x"00" severity failure;
+    rst <= '0';
+    din <= x"7e";
+    pulse;
+    assert dout = x"7e" severity failure;
+    din <= x"38";
+    en <= '0';
+    pulse;
+    assert dout = x"7e" severity failure;
+    en <= '1';
+    pulse;
+    assert dout = x"38" severity failure;
+    din <= x"27";
+    pulse;
+    assert dout = x"27" severity failure;
+    rst <= '1';
+    wait for 1 ns;
+    assert dout = x"00" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/tb_dff06.vhdl b/testsuite/synth/dff01/tb_dff06.vhdl
new file mode 100644
index 000000000..9e5274775
--- /dev/null
+++ b/testsuite/synth/dff01/tb_dff06.vhdl
@@ -0,0 +1,48 @@
+entity tb_dff06 is
+end tb_dff06;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff06 is
+  signal clk : std_logic;
+  signal din : std_logic;
+  signal dout : std_logic;
+begin
+  dut: entity work.dff06
+    port map (
+      q => dout,
+      d => din,
+      clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    din <= '0';
+    pulse;
+    pulse;
+    pulse;
+    assert dout = '0' severity failure;
+    din <= '1';
+    pulse;
+    assert dout = '0' severity failure;
+    pulse;
+    assert dout = '0' severity failure;
+    pulse;
+    assert dout = '1' severity failure;
+    din <= '0';
+    pulse;
+    assert dout = '1' severity failure;
+    pulse;
+    assert dout = '1' severity failure;
+    pulse;
+    assert dout = '0' severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/tb_dff07.vhdl b/testsuite/synth/dff01/tb_dff07.vhdl
new file mode 100644
index 000000000..67ade85a4
--- /dev/null
+++ b/testsuite/synth/dff01/tb_dff07.vhdl
@@ -0,0 +1,40 @@
+entity tb_dff07 is
+end tb_dff07;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff07 is
+  signal clk : std_logic;
+  signal din : std_logic;
+  signal dout : std_logic;
+begin
+  dut: entity work.dff07
+    port map (
+      q => dout,
+      d => din,
+      clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    din <= '0';
+    pulse;
+    assert dout = '0' severity failure;
+    din <= '1';
+    pulse;
+    assert dout = '1' severity failure;
+    pulse;
+    assert dout = '1' severity failure;
+    din <= '0';
+    pulse;
+    assert dout = '0' severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/tb_dff08.vhdl b/testsuite/synth/dff01/tb_dff08.vhdl
new file mode 100644
index 000000000..089b1e7f2
--- /dev/null
+++ b/testsuite/synth/dff01/tb_dff08.vhdl
@@ -0,0 +1,44 @@
+entity tb_dff08 is
+end tb_dff08;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff08 is
+  signal clk : std_logic;
+  signal din : std_logic;
+  signal dout : std_logic;
+begin
+  dut: entity work.dff08
+    port map (
+      q => dout,
+      d => din,
+      clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '1';
+      wait for 1 ns;
+      clk <= '0';
+      wait for 1 ns;
+    end pulse;
+  begin
+    din <= '0';
+    pulse;
+    assert dout = '0' severity failure;
+    din <= '1';
+    clk <= '1';
+    wait for 1 ns;
+    assert dout = '0' severity failure;
+    clk <= '0';
+    wait for 1 ns;
+    assert dout = '1' severity failure;
+    pulse;
+    assert dout = '1' severity failure;
+    din <= '0';
+    pulse;
+    assert dout = '0' severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/tb_dff09.vhdl b/testsuite/synth/dff01/tb_dff09.vhdl
new file mode 100644
index 000000000..87df0bb6a
--- /dev/null
+++ b/testsuite/synth/dff01/tb_dff09.vhdl
@@ -0,0 +1,47 @@
+entity tb_dff09 is
+end tb_dff09;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff09 is
+  signal clk : std_logic;
+  signal rstn : std_logic;
+  signal din : std_logic;
+  signal dout : std_logic;
+begin
+  dut: entity work.dff09
+    port map (
+      q => dout,
+      d => din,
+      clk => clk,
+      rstn => rstn);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rstn <= '0';
+    wait for 1 ns;
+    assert dout = '0' severity failure;
+    rstn <= '1';
+    din <= '1';
+    pulse;
+    assert dout = '1' severity failure;
+    din <= '0';
+    pulse;
+    assert dout = '0' severity failure;
+    din <= '1';
+    pulse;
+    assert dout = '1' severity failure;
+    rstn <= '0';
+    wait for 1 ns;
+    assert dout = '0' severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/tb_dff10.vhdl b/testsuite/synth/dff01/tb_dff10.vhdl
new file mode 100644
index 000000000..57234dc10
--- /dev/null
+++ b/testsuite/synth/dff01/tb_dff10.vhdl
@@ -0,0 +1,41 @@
+entity tb_dff10 is
+end tb_dff10;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff10 is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal din : std_logic_vector (7 downto 0);
+  signal dout : std_logic_vector (7 downto 0);
+  signal en : std_logic;
+begin
+  dut: entity work.dff10
+    port map (
+      q => dout,
+      d => din,
+      clk => clk,
+      rst => rst,
+      en => en);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    en <= '1';
+    wait for 1 ns;
+    assert dout = x"55" severity failure;
+    rst <= '0';
+    din <= x"7e";
+    pulse;
+    assert dout = x"7e" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/testsuite.sh b/testsuite/synth/dff01/testsuite.sh
index a41248549..1e0f0631c 100755
--- a/testsuite/synth/dff01/testsuite.sh
+++ b/testsuite/synth/dff01/testsuite.sh
@@ -2,17 +2,15 @@
 
 . ../../testenv.sh
 
-synth dff01.vhdl -e dff01
-synth dff02.vhdl -e dff02
-synth dff03.vhdl -e dff03
-synth dff04.vhdl -e dff04
-synth dff05.vhdl -e dff05
-synth dff06.vhdl -e dff06
-synth dff07.vhdl -e dff07
-synth dff08.vhdl -e dff08
-synth dff09.vhdl -e dff09
-synth dff10.vhdl -e dff10
+for t in dff01 dff02 dff03 dff04 dff05 dff06 dff07 dff08 dff09 dff10; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
 
-clean
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
 
 echo "Test successful"