testsuite/synth: add a test for #2142

2 files changed, 33 insertions, 0 deletions

diff --git a/testsuite/synth/issue2142/repro.vhdl b/testsuite/synth/issue2142/repro.vhdl
new file mode 100644
index 000000000..29cbef82c
--- /dev/null
+++ b/testsuite/synth/issue2142/repro.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity repro is
+  port (radr : unsigned (0 downto 0);
+        v : out std_logic_vector(7 downto 0);
+        we : std_logic;
+        clk : std_logic);
+end repro;
+
+architecture behav of repro is
+  type t_mem is array (0 to 0) of std_logic_vector(7 downto 0);
+  signal m : t_mem;
+begin
+  process (clk)
+  begin
+    if rising_edge (clk) then
+      if we = '1' then
+        m(0) <= not m(0);
+      else
+        v <= m (to_integer (radr));
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue2142/testsuite.sh b/testsuite/synth/issue2142/testsuite.sh
new file mode 100755
index 000000000..e9dc72228
--- /dev/null
+++ b/testsuite/synth/issue2142/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_only repro
+
+echo "Test successful"