testsuite/mem02: add more tests for RAM inference.

13 files changed, 544 insertions, 1 deletions

diff --git a/testsuite/synth/mem02/dpram2.vhdl b/testsuite/synth/mem02/dpram2.vhdl
new file mode 100644
index 000000000..d7e98d6b7
--- /dev/null
+++ b/testsuite/synth/mem02/dpram2.vhdl
@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dpram1 is
+  port (raddr : std_logic_vector (3 downto 0);
+        rdat : out std_logic_vector (7 downto 0);
+        waddr : std_logic_vector (3 downto 0);
+        wdat : std_logic_vector (7 downto 0);
+        clk : std_logic);
+end dpram1;
+
+architecture behav of dpram1 is
+  subtype memtype is std_logic_vector (16 * 8 - 1 downto 0);
+  signal mem : memtype;
+begin
+  process (clk)
+    variable ra : natural;
+    variable wa : natural;
+    variable rlo, rhi : natural;
+  begin
+    if rising_edge (clk) then
+      ra := to_integer(unsigned (raddr));
+      rlo := ra * 8;
+      rhi := rlo + 7;
+      rdat <= mem (rhi downto rlo);
+      wa := to_integer(unsigned (waddr));
+      mem (wa * 8 + 7 downto wa * 8) <= wdat;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem02/dpram3.vhdl b/testsuite/synth/mem02/dpram3.vhdl
new file mode 100644
index 000000000..d57476362
--- /dev/null
+++ b/testsuite/synth/mem02/dpram3.vhdl
@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dpram3 is
+  port (raddr : std_logic_vector (3 downto 0);
+        rdat : out std_logic_vector (7 downto 0);
+        waddr : std_logic_vector (3 downto 0);
+        wdat : std_logic_vector (7 downto 0);
+        rclk : std_logic;
+        wclk : std_logic);
+end;
+
+architecture behav of dpram3 is
+  subtype memtype is std_logic_vector (16 * 8 - 1 downto 0);
+  signal mem : memtype;
+begin
+  process (rclk, wclk)
+    variable ra : natural;
+    variable wa : natural;
+  begin
+    if rising_edge (rclk) then
+      ra := to_integer(unsigned (raddr));
+      rdat <= mem (ra * 8 + 7 downto ra * 8);
+    end if;
+    if rising_edge(wclk) then
+      wa := to_integer(unsigned (waddr));
+      mem (wa * 8 + 7 downto wa * 8) <= wdat;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem02/dpram4.vhdl b/testsuite/synth/mem02/dpram4.vhdl
new file mode 100644
index 000000000..668841eb3
--- /dev/null
+++ b/testsuite/synth/mem02/dpram4.vhdl
@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dpram4 is
+  port (raddr : std_logic_vector (3 downto 0);
+        rdat : out std_logic_vector (7 downto 0);
+        waddr : std_logic_vector (3 downto 0);
+        wdat : std_logic_vector (7 downto 0);
+        rclk : std_logic;
+        wclk : std_logic);
+end;
+
+architecture behav of dpram4 is
+  subtype memtype is std_logic_vector (16 * 8 - 1 downto 0);
+begin
+  process (rclk, wclk)
+    variable ra : natural;
+    variable wa : natural;
+    variable mem : memtype;
+  begin
+    if rising_edge (rclk) then
+      ra := to_integer(unsigned (raddr));
+      rdat <= mem (ra * 8 + 7 downto ra * 8);
+    end if;
+    if rising_edge(wclk) then
+      wa := to_integer(unsigned (waddr));
+      mem (wa * 8 + 7 downto wa * 8) := wdat;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem02/dpram5.vhdl b/testsuite/synth/mem02/dpram5.vhdl
new file mode 100644
index 000000000..32d0be04d
--- /dev/null
+++ b/testsuite/synth/mem02/dpram5.vhdl
@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dpram5 is
+  port (raddr : std_logic_vector (3 downto 0);
+        rdat : out std_logic_vector (7 downto 0);
+        waddr : std_logic_vector (3 downto 0);
+        wdat : std_logic_vector (7 downto 0);
+        rclk : std_logic;
+        wclk : std_logic);
+end;
+
+architecture behav of dpram5 is
+  subtype memtype is std_logic_vector (16 * 8 - 1 downto 0);
+begin
+  process (rclk, wclk)
+    variable ra : natural;
+    variable wa : natural;
+    variable mem : memtype;
+  begin
+    if rising_edge(wclk) then
+      wa := to_integer(unsigned (waddr));
+      mem (wa * 8 + 7 downto wa * 8) := wdat;
+    end if;
+    if rising_edge (rclk) then
+      ra := to_integer(unsigned (raddr));
+      rdat <= mem (ra * 8 + 7 downto ra * 8);
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem02/dpram6.vhdl b/testsuite/synth/mem02/dpram6.vhdl
new file mode 100644
index 000000000..cd759bf09
--- /dev/null
+++ b/testsuite/synth/mem02/dpram6.vhdl
@@ -0,0 +1,32 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dpram6 is
+  port (raddr : std_logic_vector (3 downto 0);
+        rdat : out std_logic_vector (7 downto 0);
+        waddr : std_logic_vector (3 downto 0);
+        wdat : std_logic_vector (7 downto 0);
+        clk : std_logic);
+end;
+
+architecture behav of dpram6 is
+  subtype memtype is std_logic_vector (16 * 8 - 1 downto 0);
+begin
+  process (clk)
+    variable ra : natural;
+    variable wa : natural;
+    variable mem : memtype;
+  begin
+    --  Not correct (?)
+    --  Synthesized netlist is parallel while this code is sequential.
+    if rising_edge(clk) then
+      wa := to_integer(unsigned (waddr));
+      mem (wa * 8 + 7 downto wa * 8) := wdat;
+    end if;
+    if rising_edge (clk) then
+      ra := to_integer(unsigned (raddr));
+      rdat <= mem (ra * 8 + 7 downto ra * 8);
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem02/dpram7.vhdl b/testsuite/synth/mem02/dpram7.vhdl
new file mode 100644
index 000000000..d6d4d4247
--- /dev/null
+++ b/testsuite/synth/mem02/dpram7.vhdl
@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dpram7 is
+  port (raddr : std_logic_vector (3 downto 0);
+        rdat : out std_logic_vector (7 downto 0);
+        waddr1 : std_logic_vector (3 downto 0);
+        wdat1 : std_logic_vector (7 downto 0);
+        waddr2 : std_logic_vector (3 downto 0);
+        wdat2 : std_logic_vector (7 downto 0);
+        rclk : std_logic;
+        wclk : std_logic);
+end;
+
+architecture behav of dpram7 is
+  subtype memtype is std_logic_vector (16 * 8 - 1 downto 0);
+begin
+  process (rclk, wclk)
+    variable ra : natural;
+    variable wa : natural;
+    variable mem : memtype;
+  begin
+    if rising_edge(wclk) then
+      wa := to_integer(unsigned (waddr1));
+      mem (wa * 8 + 7 downto wa * 8) := wdat1;
+      wa := to_integer(unsigned (waddr2));
+      mem (wa * 8 + 7 downto wa * 8) := wdat2;
+    end if;
+    if rising_edge (rclk) then
+      ra := to_integer(unsigned (raddr));
+      rdat <= mem (ra * 8 + 7 downto ra * 8);
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem02/dpram8.vhdl b/testsuite/synth/mem02/dpram8.vhdl
new file mode 100644
index 000000000..9a0f38daf
--- /dev/null
+++ b/testsuite/synth/mem02/dpram8.vhdl
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dpram8 is
+  port (raddr : std_logic_vector (3 downto 0);
+        rdat : out std_logic_vector (7 downto 0);
+        waddr1 : std_logic_vector (3 downto 0);
+        wdat1 : std_logic_vector (7 downto 0);
+        waddr2 : std_logic_vector (3 downto 0);
+        wdat2 : std_logic_vector (7 downto 0);
+        rclk : std_logic;
+        wclk1 : std_logic;
+        wclk2 : std_logic);
+end;
+
+architecture behav of dpram8 is
+  subtype memtype is std_logic_vector (16 * 8 - 1 downto 0);
+begin
+  process (rclk, wclk1, wclk2)
+    variable ra : natural;
+    variable wa : natural;
+    variable mem : memtype;
+  begin
+    if rising_edge(wclk1) then
+      wa := to_integer(unsigned (waddr1));
+      mem (wa * 8 + 7 downto wa * 8) := wdat1;
+    end if;
+    if rising_edge(wclk2) then
+      wa := to_integer(unsigned (waddr2));
+      mem (wa * 8 + 7 downto wa * 8) := wdat2;
+    end if;
+    if rising_edge (rclk) then
+      ra := to_integer(unsigned (raddr));
+      rdat <= mem (ra * 8 + 7 downto ra * 8);
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem02/tb_dpram3.vhdl b/testsuite/synth/mem02/tb_dpram3.vhdl
new file mode 100644
index 000000000..e04ea8fe7
--- /dev/null
+++ b/testsuite/synth/mem02/tb_dpram3.vhdl
@@ -0,0 +1,51 @@
+entity tb_dpram3 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dpram3 is
+  signal raddr : std_logic_vector(3 downto 0);
+  signal rdat : std_logic_vector(7 downto 0);
+  signal waddr : std_logic_vector(3 downto 0);
+  signal wdat : std_logic_vector(7 downto 0);
+  signal rclk, wclk : std_logic;
+begin
+  dut: entity work.dpram3
+    port map (raddr => raddr, rdat => rdat, waddr => waddr, wdat => wdat,
+              rclk => rclk, wclk => wclk);
+
+  process
+    procedure rpulse is
+    begin
+      rclk <= '0';
+      wait for 1 ns;
+      rclk <= '1';
+      wait for 1 ns;
+    end rpulse;
+
+    procedure wpulse is
+    begin
+      wclk <= '0';
+      wait for 1 ns;
+      wclk <= '1';
+      wait for 1 ns;
+    end wpulse;
+  begin
+    raddr <= "0000";
+    waddr <= "0001";
+    wdat <= x"01";
+    wpulse;
+
+    raddr <= "0001";
+    rpulse;
+    assert rdat = x"01" severity failure;
+
+    waddr <= "0010";
+    wdat <= x"02";
+    wpulse;
+    assert rdat = x"01" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem02/tb_dpram4.vhdl b/testsuite/synth/mem02/tb_dpram4.vhdl
new file mode 100644
index 000000000..8878ee061
--- /dev/null
+++ b/testsuite/synth/mem02/tb_dpram4.vhdl
@@ -0,0 +1,51 @@
+entity tb_dpram4 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dpram4 is
+  signal raddr : std_logic_vector(3 downto 0);
+  signal rdat : std_logic_vector(7 downto 0);
+  signal waddr : std_logic_vector(3 downto 0);
+  signal wdat : std_logic_vector(7 downto 0);
+  signal rclk, wclk : std_logic;
+begin
+  dut: entity work.dpram4
+    port map (raddr => raddr, rdat => rdat, waddr => waddr, wdat => wdat,
+              rclk => rclk, wclk => wclk);
+
+  process
+    procedure rpulse is
+    begin
+      rclk <= '0';
+      wait for 1 ns;
+      rclk <= '1';
+      wait for 1 ns;
+    end rpulse;
+
+    procedure wpulse is
+    begin
+      wclk <= '0';
+      wait for 1 ns;
+      wclk <= '1';
+      wait for 1 ns;
+    end wpulse;
+  begin
+    raddr <= "0000";
+    waddr <= "0001";
+    wdat <= x"01";
+    wpulse;
+
+    raddr <= "0001";
+    rpulse;
+    assert rdat = x"01" severity failure;
+
+    waddr <= "0010";
+    wdat <= x"02";
+    wpulse;
+    assert rdat = x"01" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem02/tb_dpram5.vhdl b/testsuite/synth/mem02/tb_dpram5.vhdl
new file mode 100644
index 000000000..c12125831
--- /dev/null
+++ b/testsuite/synth/mem02/tb_dpram5.vhdl
@@ -0,0 +1,51 @@
+entity tb_dpram5 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dpram5 is
+  signal raddr : std_logic_vector(3 downto 0);
+  signal rdat : std_logic_vector(7 downto 0);
+  signal waddr : std_logic_vector(3 downto 0);
+  signal wdat : std_logic_vector(7 downto 0);
+  signal rclk, wclk : std_logic;
+begin
+  dut: entity work.dpram5
+    port map (raddr => raddr, rdat => rdat, waddr => waddr, wdat => wdat,
+              rclk => rclk, wclk => wclk);
+
+  process
+    procedure rpulse is
+    begin
+      rclk <= '0';
+      wait for 1 ns;
+      rclk <= '1';
+      wait for 1 ns;
+    end rpulse;
+
+    procedure wpulse is
+    begin
+      wclk <= '0';
+      wait for 1 ns;
+      wclk <= '1';
+      wait for 1 ns;
+    end wpulse;
+  begin
+    raddr <= "0000";
+    waddr <= "0001";
+    wdat <= x"01";
+    wpulse;
+
+    raddr <= "0001";
+    rpulse;
+    assert rdat = x"01" severity failure;
+
+    waddr <= "0010";
+    wdat <= x"02";
+    wpulse;
+    assert rdat = x"01" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem02/tb_dpram7.vhdl b/testsuite/synth/mem02/tb_dpram7.vhdl
new file mode 100644
index 000000000..dc32803f4
--- /dev/null
+++ b/testsuite/synth/mem02/tb_dpram7.vhdl
@@ -0,0 +1,66 @@
+entity tb_dpram7 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dpram7 is
+  signal raddr : std_logic_vector(3 downto 0);
+  signal rdat : std_logic_vector(7 downto 0);
+  signal waddr1 : std_logic_vector(3 downto 0);
+  signal wdat1 : std_logic_vector(7 downto 0);
+  signal waddr2 : std_logic_vector(3 downto 0);
+  signal wdat2 : std_logic_vector(7 downto 0);
+  signal rclk, wclk : std_logic;
+begin
+  dut: entity work.dpram7
+    port map (raddr => raddr, rdat => rdat,
+              waddr1 => waddr1, wdat1 => wdat1,
+              waddr2 => waddr2, wdat2 => wdat2,
+              rclk => rclk, wclk => wclk);
+
+  process
+    procedure rpulse is
+    begin
+      rclk <= '0';
+      wait for 1 ns;
+      rclk <= '1';
+      wait for 1 ns;
+    end rpulse;
+
+    procedure wpulse is
+    begin
+      wclk <= '0';
+      wait for 1 ns;
+      wclk <= '1';
+      wait for 1 ns;
+    end wpulse;
+  begin
+    raddr <= "0000";
+    waddr1 <= "0001";
+    waddr2 <= "0010";
+    wdat1 <= x"01";
+    wdat2 <= x"02";
+    wpulse;
+
+    raddr <= "0001";
+    rpulse;
+    assert rdat = x"01" severity failure;
+
+    raddr <= "0010";
+    rpulse;
+    assert rdat = x"02" severity failure;
+
+    waddr1 <= "0011";
+    wdat1 <= x"03";
+    raddr <= "0001";
+    wpulse;
+    assert rdat = x"02" severity failure;
+
+    raddr <= "0011";
+    rpulse;
+    assert rdat = x"03" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem02/tb_dpram8.vhdl b/testsuite/synth/mem02/tb_dpram8.vhdl
new file mode 100644
index 000000000..8f99e3e31
--- /dev/null
+++ b/testsuite/synth/mem02/tb_dpram8.vhdl
@@ -0,0 +1,95 @@
+entity tb_dpram8 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dpram8 is
+  signal raddr : std_logic_vector(3 downto 0);
+  signal rdat : std_logic_vector(7 downto 0);
+  signal waddr1 : std_logic_vector(3 downto 0);
+  signal wdat1 : std_logic_vector(7 downto 0);
+  signal waddr2 : std_logic_vector(3 downto 0);
+  signal wdat2 : std_logic_vector(7 downto 0);
+  signal rclk, wclk1, wclk2 : std_logic;
+begin
+  dut: entity work.dpram8
+    port map (raddr => raddr, rdat => rdat,
+              waddr1 => waddr1, wdat1 => wdat1,
+              waddr2 => waddr2, wdat2 => wdat2,
+              rclk => rclk, wclk1 => wclk1, wclk2 => wclk2);
+
+  process
+    procedure rpulse is
+    begin
+      rclk <= '0';
+      wait for 1 ns;
+      rclk <= '1';
+      wait for 1 ns;
+    end rpulse;
+
+    procedure wpulse1 is
+    begin
+      wclk1 <= '0';
+      wait for 1 ns;
+      wclk1 <= '1';
+      wait for 1 ns;
+    end wpulse1;
+
+    procedure wpulse2 is
+    begin
+      wclk2 <= '0';
+      wait for 1 ns;
+      wclk2 <= '1';
+      wait for 1 ns;
+    end wpulse2;
+  begin
+    --  Test write port 1
+    raddr <= "0000";
+    waddr1 <= "0001";
+    wdat1 <= x"01";
+    wpulse1;
+
+    raddr <= "0001";
+    rpulse;
+    assert rdat = x"01" severity failure;
+
+    --  Test write port 2.
+    waddr2 <= "0010";
+    wdat2 <= x"02";
+    wdat1 <= x"ff";
+    wpulse2;
+
+    --  Check write port 2 doesn't affect read port.
+    assert rdat = x"01" severity failure;
+
+    --  Check write port 2 action.
+    raddr <= "0010";
+    rpulse;
+    assert rdat = x"02" severity failure;
+
+    --  Check no change for write port 1.
+    raddr <= "0001";
+    rpulse;
+    assert rdat = x"01" severity failure;
+
+    --  Check write port 1 doesn't affect read port.
+    waddr1 <= "0011";
+    wdat1 <= x"03";
+    raddr <= "0001";
+    wdat2 <= x"ff";
+    wpulse1;
+    assert rdat = x"01" severity failure;
+
+    raddr <= "0011";
+    rpulse;
+    assert rdat = x"03" severity failure;
+
+    --  And write port 1 doesn't affect write port 2.
+    raddr <= "0010";
+    rpulse;
+    assert rdat = x"02" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem02/testsuite.sh b/testsuite/synth/mem02/testsuite.sh
index 1250b3f39..8f6c0691d 100755
--- a/testsuite/synth/mem02/testsuite.sh
+++ b/testsuite/synth/mem02/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in dpram1; do
+for t in dpram1 dpram3 dpram4 dpram5 dpram7 dpram8; do
     synth_tb $t 2> $t.log
     grep "found R" $t.log
 done