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| author | Tristan Gingold <tgingold@free.fr> | 2021-08-29 07:28:45 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-08-29 11:50:17 +0200 |
| commit | 2d1dda579d0f47fa71fa0dedf60a1a1c29177d34 (patch) | |
| tree | c2e0f68852c6c12f1949eefdd1bf7d8f244a42f9 /testsuite/synth | |
| parent | 2b8e100539fbbf2c27a6acbc9905ba50b0f352b1 (diff) | |
| download | ghdl-2d1dda579d0f47fa71fa0dedf60a1a1c29177d34.tar.gz ghdl-2d1dda579d0f47fa71fa0dedf60a1a1c29177d34.tar.bz2 ghdl-2d1dda579d0f47fa71fa0dedf60a1a1c29177d34.zip | |
testsuite/synth: add a test for #1832
Diffstat (limited to 'testsuite/synth')
| -rw-r--r-- | testsuite/synth/issue1832/issue.vhdl | 21 | ||||
| -rwxr-xr-x | testsuite/synth/issue1832/testsuite.sh | 8 |
2 files changed, 29 insertions, 0 deletions
diff --git a/testsuite/synth/issue1832/issue.vhdl b/testsuite/synth/issue1832/issue.vhdl new file mode 100644 index 000000000..4d005d5ef --- /dev/null +++ b/testsuite/synth/issue1832/issue.vhdl @@ -0,0 +1,21 @@ +library ieee; + use ieee.std_logic_1164.all; + + +entity issue is + port ( + clk : in std_logic; + a, b : in std_logic + ); +end entity issue; + + +architecture psl of issue is +begin + + -- All is sensitive to rising edge of clk + default clock is rising_edge(clk); + + -- This assertion should hold + INF_a : assert always {a} |=> {not b[*0 to inf]; b}; +end architecture psl; diff --git a/testsuite/synth/issue1832/testsuite.sh b/testsuite/synth/issue1832/testsuite.sh new file mode 100755 index 000000000..bec350d37 --- /dev/null +++ b/testsuite/synth/issue1832/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth_only issue + +echo "Test successful" |