testsuite/synth: add a test. close #2080

3 files changed, 62 insertions, 0 deletions

diff --git a/testsuite/synth/issue2080/ent.vhdl b/testsuite/synth/issue2080/ent.vhdl
new file mode 100644
index 000000000..d667ddfe0
--- /dev/null
+++ b/testsuite/synth/issue2080/ent.vhdl
@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity identity is
+	port (
+		x: in std_logic_vector(7 downto 0);
+		y: out std_logic_vector(7 downto 0)
+	);
+end entity;
+
+architecture a of identity is
+begin
+	y <= x;
+end architecture;
+
+---
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+	port (
+		a: in std_logic_vector(7 downto 0);
+		b: out std_logic_vector(7 downto 0)
+	);
+end entity;
+
+architecture a of ent is
+	function transform(val: std_logic_vector) return std_logic_vector is
+	begin
+		return (7 downto 0 => '0');
+	end function;
+begin
+	identity: entity work.identity port map (x => transform(a), y => b);
+end architecture;
diff --git a/testsuite/synth/issue2080/tb_ent.vhdl b/testsuite/synth/issue2080/tb_ent.vhdl
new file mode 100644
index 000000000..d9aed6d71
--- /dev/null
+++ b/testsuite/synth/issue2080/tb_ent.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb_ent is
+end entity;
+
+architecture a of tb_ent is
+	signal a, b : std_logic_vector(7 downto 0);
+begin
+	uut: entity work.ent port map (a => a, b => b);
+
+	process
+	begin
+		a <= x"42";
+		wait for 1 ns;
+		assert b = x"00";
+
+		wait;
+	end process;
+end architecture;
diff --git a/testsuite/synth/issue2080/testsuite.sh b/testsuite/synth/issue2080/testsuite.sh
new file mode 100755
index 000000000..5c1da263d
--- /dev/null
+++ b/testsuite/synth/issue2080/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_tb ent
+
+echo "Test successful"