testsuite/synth: add synth48

1 files changed, 21 insertions, 0 deletions

diff --git a/testsuite/synth/synth48/test.vhdl b/testsuite/synth/synth48/test.vhdl
new file mode 100644
index 000000000..d04d6673f
--- /dev/null
+++ b/testsuite/synth/synth48/test.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity test is
+  port (
+    Reset_n_i    : in  std_logic;
+    Clk_i        : in  std_logic
+  );
+end entity test;
+
+
+architecture beh of test is
+begin
+
+  default clock is rising_edge(Clk_i);
+  restrict {Reset_n_i = '0'[*5]; Reset_n_i = '1'[+]}[*1];
+
+end architecture beh;
+