testsuite/synth: improve test for previous commit.

2 files changed, 40 insertions, 4 deletions

diff --git a/testsuite/synth/synth38/tb_modulo_test.vhdl b/testsuite/synth/synth38/tb_modulo_test.vhdl
new file mode 100644
index 000000000..0395be47a
--- /dev/null
+++ b/testsuite/synth/synth38/tb_modulo_test.vhdl
@@ -0,0 +1,31 @@
+entity tb_modulo_test is
+end tb_modulo_test;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_modulo_test is
+  signal a, b, c : integer := 0;
+begin
+  dut: entity work.modulo_test
+    port map (a, b, c);
+
+  process
+  begin
+    a <= 7;
+    wait for 1 ns;
+    assert b = 7 severity failure;
+    assert c = 7 severity failure;
+    
+    a <= 8;
+    wait for 1 ns;
+    assert b = 0 severity failure;
+    assert c = 0 severity failure;
+
+    a <= -7;
+    wait for 1 ns;
+    assert b = 1 severity failure;
+    assert c = -7 severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/synth38/testsuite.sh b/testsuite/synth/synth38/testsuite.sh
index 243a72f8b..8fbbd24ae 100755
--- a/testsuite/synth/synth38/testsuite.sh
+++ b/testsuite/synth/synth38/testsuite.sh
@@ -2,10 +2,15 @@
 
 . ../../testenv.sh
 
-for f in modulo_test; do
-  synth $f.vhdl -e $f > syn_$f.vhdl
-#  analyze syn_$f.vhdl
+for t in modulo_test; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
 done
-clean
 
 echo "Test successful"