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| author | Tristan Gingold <tgingold@free.fr> | 2019-09-25 20:39:46 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-09-25 20:39:46 +0200 |
| commit | 6e9336d11dfc4f53dba234e1f02a2b0172461e0c (patch) | |
| tree | 12f93ed2cbbb62c0e8e2fb6b7124201fe0a216bd /testsuite/synth/synth34/repro_slv.vhdl | |
| parent | dcc353b07b82a84f2aa598de3884c58f406e0652 (diff) | |
| download | ghdl-6e9336d11dfc4f53dba234e1f02a2b0172461e0c.tar.gz ghdl-6e9336d11dfc4f53dba234e1f02a2b0172461e0c.tar.bz2 ghdl-6e9336d11dfc4f53dba234e1f02a2b0172461e0c.zip | |
testsuite/synth: rename issueXX to synthXX for ghdlsynth-beta issues.
Diffstat (limited to 'testsuite/synth/synth34/repro_slv.vhdl')
| -rw-r--r-- | testsuite/synth/synth34/repro_slv.vhdl | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/testsuite/synth/synth34/repro_slv.vhdl b/testsuite/synth/synth34/repro_slv.vhdl new file mode 100644 index 000000000..4b0e1b0e5 --- /dev/null +++ b/testsuite/synth/synth34/repro_slv.vhdl @@ -0,0 +1,42 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity sub_slv is + port ( + clk : in std_logic; + a : in std_logic_vector(7 downto 0); + b : out std_logic_vector(7 downto 0) + ); +end sub_slv; + +architecture rtl of sub_slv is +begin + process(clk) + begin + if rising_edge(clk) then + b <= a; + end if; + end process; +end rtl; + + +library ieee; + use ieee.std_logic_1164.all; + +entity repro_slv is + port ( + clk : in std_logic; + a : in std_logic_vector(7 downto 0); + b : out std_logic_vector(7 downto 0) + ); +end repro_slv; + +architecture rtl of repro_slv is +begin + i_sub_slv : entity work.sub_slv + port map ( + clk => clk, + a => a, + b => b + ); +end rtl; |