testsuite/synth: rename issueXX to synthXX for ghdlsynth-beta issues.

3 files changed, 73 insertions, 0 deletions

diff --git a/testsuite/synth/synth33/int_test.vhdl b/testsuite/synth/synth33/int_test.vhdl
new file mode 100644
index 000000000..62ea65bda
--- /dev/null
+++ b/testsuite/synth/synth33/int_test.vhdl
@@ -0,0 +1,31 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity int_test is
+  generic (
+    INT_MIN : integer range 1 to 8 := 1;
+    INT_MAX : integer range 1 to 8 := 8
+  );
+  port (
+    clk : in std_logic;
+    a : in integer range INT_MIN to INT_MAX;
+    b : out integer range INT_MIN to INT_MAX
+  );
+end int_test;
+
+architecture rtl of int_test is
+  signal int : integer range INT_MIN to INT_MAX;
+begin
+  process (clk)
+  begin
+    if rising_edge (clk) then
+      if a < INT_MAX then
+        int <= a + 1;
+      else
+        int <= INT_MIN;
+      end if;
+    end if;
+  end process;
+  b <= int;
+end rtl;
+
diff --git a/testsuite/synth/synth33/int_test2.vhdl b/testsuite/synth/synth33/int_test2.vhdl
new file mode 100644
index 000000000..eb43306c4
--- /dev/null
+++ b/testsuite/synth/synth33/int_test2.vhdl
@@ -0,0 +1,31 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity int_test2 is
+  generic (
+    INT_MIN : integer range 1 to 8 := 1;
+    INT_MAX : integer range 1 to 8 := 8
+  );
+  port (
+    clk : in std_logic;
+    a : in integer range INT_MIN to INT_MAX;
+    b : out integer range INT_MIN to INT_MAX
+  );
+end int_test2;
+
+architecture rtl of int_test2 is
+  signal int : integer range INT_MIN to INT_MAX;
+begin
+  process (clk)
+  begin
+    if rising_edge (clk) then
+      if a < INT_MAX then
+        int <= a + 1;
+      else
+        int <= INT_MIN * 2;
+      end if;
+    end if;
+  end process;
+  b <= int;
+end rtl;
+
diff --git a/testsuite/synth/synth33/testsuite.sh b/testsuite/synth/synth33/testsuite.sh
new file mode 100755
index 000000000..fca6f7d69
--- /dev/null
+++ b/testsuite/synth/synth33/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in int_test int_test2; do
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl
+    clean
+done
+
+echo "Test successful"