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author | Tristan Gingold <tgingold@free.fr> | 2019-09-25 20:39:46 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-25 20:39:46 +0200 |
commit | 6e9336d11dfc4f53dba234e1f02a2b0172461e0c (patch) | |
tree | 12f93ed2cbbb62c0e8e2fb6b7124201fe0a216bd /testsuite/synth/synth26 | |
parent | dcc353b07b82a84f2aa598de3884c58f406e0652 (diff) | |
download | ghdl-6e9336d11dfc4f53dba234e1f02a2b0172461e0c.tar.gz ghdl-6e9336d11dfc4f53dba234e1f02a2b0172461e0c.tar.bz2 ghdl-6e9336d11dfc4f53dba234e1f02a2b0172461e0c.zip |
testsuite/synth: rename issueXX to synthXX for ghdlsynth-beta issues.
Diffstat (limited to 'testsuite/synth/synth26')
-rw-r--r-- | testsuite/synth/synth26/int_test.vhdl | 20 | ||||
-rwxr-xr-x | testsuite/synth/synth26/testsuite.sh | 9 |
2 files changed, 29 insertions, 0 deletions
diff --git a/testsuite/synth/synth26/int_test.vhdl b/testsuite/synth/synth26/int_test.vhdl new file mode 100644 index 000000000..afc8c4cdb --- /dev/null +++ b/testsuite/synth/synth26/int_test.vhdl @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity int_test is + port (clk : in std_logic; + a, b : in integer range 0 to 1; + c : out std_logic); +end int_test; + +architecture rtl of int_test is +begin + process (clk) + begin + if rising_edge (clk) then + if a < b then + c <= '0'; + end if; + end if; + end process; +end rtl; diff --git a/testsuite/synth/synth26/testsuite.sh b/testsuite/synth/synth26/testsuite.sh new file mode 100755 index 000000000..1cc0536d7 --- /dev/null +++ b/testsuite/synth/synth26/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +synth int_test.vhdl -e int_test > syn_int_test.vhdl +analyze syn_int_test.vhdl +clean + +echo "Test successful" |