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authorTristan Gingold <tgingold@free.fr>2019-09-25 20:39:46 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-25 20:39:46 +0200
commit6e9336d11dfc4f53dba234e1f02a2b0172461e0c (patch)
tree12f93ed2cbbb62c0e8e2fb6b7124201fe0a216bd /testsuite/synth/synth12/tb_lut.vhdl
parentdcc353b07b82a84f2aa598de3884c58f406e0652 (diff)
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testsuite/synth: rename issueXX to synthXX for ghdlsynth-beta issues.
Diffstat (limited to 'testsuite/synth/synth12/tb_lut.vhdl')
-rw-r--r--testsuite/synth/synth12/tb_lut.vhdl34
1 files changed, 34 insertions, 0 deletions
diff --git a/testsuite/synth/synth12/tb_lut.vhdl b/testsuite/synth/synth12/tb_lut.vhdl
new file mode 100644
index 000000000..f8f5cf3a6
--- /dev/null
+++ b/testsuite/synth/synth12/tb_lut.vhdl
@@ -0,0 +1,34 @@
+entity tb_lut is
+end tb_lut;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_lut is
+ signal c : std_logic;
+ signal s : std_logic_vector(1 downto 0);
+begin
+ dut: entity work.lut
+ port map (s, c);
+
+ process
+ begin
+ s <= "00";
+ wait for 1 ns;
+ assert c = '1' severity failure;
+
+ s <= "01";
+ wait for 1 ns;
+ assert c = '0' severity failure;
+
+ s <= "10";
+ wait for 1 ns;
+ assert c = '1' severity failure;
+
+ s <= "11";
+ wait for 1 ns;
+ assert c = '0' severity failure;
+
+ wait;
+ end process;
+end behav;