testsuite/synth: add a test for previous commit.

3 files changed, 67 insertions, 9 deletions

diff --git a/testsuite/synth/subprg01/subprg02.vhdl b/testsuite/synth/subprg01/subprg02.vhdl
new file mode 100644
index 000000000..76a2ba381
--- /dev/null
+++ b/testsuite/synth/subprg01/subprg02.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity subprg02 is
+  port (a : std_logic_vector (3 downto 0);
+        n : natural range 0 to 1;
+        clk : std_logic;
+        na : out std_logic_vector (3 downto 0));
+end subprg02;
+
+architecture behav of subprg02 is
+  procedure neg (v : inout std_logic_vector(3 downto 0)) is
+  begin
+    v := not v;
+  end neg;
+
+begin
+  process(clk)
+    type t_arr is array (natural range <>) of std_logic_vector(3 downto 0);
+    variable mem : t_arr (0 to 1);
+  begin
+    if rising_edge (clk) then
+      mem (n) := a;
+      neg (mem (n));
+      na <= mem (n);
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/subprg01/tb_subprg02.vhdl b/testsuite/synth/subprg01/tb_subprg02.vhdl
new file mode 100644
index 000000000..0736990a7
--- /dev/null
+++ b/testsuite/synth/subprg01/tb_subprg02.vhdl
@@ -0,0 +1,37 @@
+entity tb_subprg02 is
+end tb_subprg02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_subprg02 is
+  signal a, na : std_logic_vector (3 downto 0);
+  signal n : natural range 0 to 1;
+  signal clk : std_logic;
+begin
+  dut: entity work.subprg02
+    port map (a, n, clk, na);
+
+  process
+    procedure pulse is
+    begin
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+      clk <= '0';
+    end pulse;
+  begin
+    n <= 0;
+    clk <= '0';
+
+    a <= x"0";
+    pulse;
+    assert na = x"f" severity failure;
+
+    a <= x"5";
+    pulse;
+    assert na = x"a" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/subprg01/testsuite.sh b/testsuite/synth/subprg01/testsuite.sh
index 82e200888..a9a3f3f9f 100755
--- a/testsuite/synth/subprg01/testsuite.sh
+++ b/testsuite/synth/subprg01/testsuite.sh
@@ -2,15 +2,8 @@
 
 . ../../testenv.sh
 
-for t in subprg01; do
-    analyze $t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
-    clean
-
-    synth $t.vhdl -e $t > syn_$t.vhdl
-    analyze syn_$t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t --ieee-asserts=disable-at-0
-    clean
+for t in subprg01 subprg02; do
+    synth_tb $t
 done
 
 echo "Test successful"