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author | Tristan Gingold <tgingold@free.fr> | 2020-08-07 21:54:09 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-08-07 21:55:53 +0200 |
commit | a18e1503a9896152268705aab21a6ee491756ff7 (patch) | |
tree | 7fd8a8fe8ca3cfca8687c6c2fe26e2224c712cf1 /testsuite/synth/snsuns01/umuls.vhdl | |
parent | b46d4db8b112d40b056c102d65a64d08a00f4668 (diff) | |
download | ghdl-a18e1503a9896152268705aab21a6ee491756ff7.tar.gz ghdl-a18e1503a9896152268705aab21a6ee491756ff7.tar.bz2 ghdl-a18e1503a9896152268705aab21a6ee491756ff7.zip |
testsuite/synth: add tests for std_logic_unsigned and std_logic_signed.
Diffstat (limited to 'testsuite/synth/snsuns01/umuls.vhdl')
-rw-r--r-- | testsuite/synth/snsuns01/umuls.vhdl | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/testsuite/synth/snsuns01/umuls.vhdl b/testsuite/synth/snsuns01/umuls.vhdl new file mode 100644 index 000000000..57971d214 --- /dev/null +++ b/testsuite/synth/snsuns01/umuls.vhdl @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity muls is + port ( + l3 : std_logic_vector (2 downto 0); + r4 : std_logic_vector (3 downto 0); + + mul_v3v4 : out std_logic_vector (6 downto 0)); +end muls; + +library ieee; +use ieee.std_logic_unsigned.all; + +architecture behav of muls is +begin + mul_v3v4 <= l3 * r4; +end behav; |