testsuite/synth: add a simple test for std_logic_arith.

2 files changed, 31 insertions, 0 deletions

diff --git a/testsuite/synth/sns01/sns01.vhdl b/testsuite/synth/sns01/sns01.vhdl
new file mode 100644
index 000000000..a8f3b7e60
--- /dev/null
+++ b/testsuite/synth/sns01/sns01.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity sns01 is
+  port (a : natural range 0 to 15;
+        b : out unsigned (3 downto 0);
+        clk : std_logic);
+end sns01;
+
+architecture behav of sns01 is
+begin
+  process (clk)
+  begin
+    if rising_edge(clk) then
+      b <= conv_unsigned (a, 4);
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/sns01/testsuite.sh b/testsuite/synth/sns01/testsuite.sh
new file mode 100755
index 000000000..2f17c5d8f
--- /dev/null
+++ b/testsuite/synth/sns01/testsuite.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--ieee=synopsys
+for t in sns01; do
+    synth $t.vhdl -e $t > syn_$t.vhdl
+#    analyze syn_$t.vhdl
+    clean
+done
+
+echo "Test successful"