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authorTristan Gingold <tgingold@free.fr>2020-08-07 21:49:31 +0200
committerTristan Gingold <tgingold@free.fr>2020-08-07 21:55:53 +0200
commitb46d4db8b112d40b056c102d65a64d08a00f4668 (patch)
tree54ba3e0fd138d8f8c0bc34826556555b41ee01fa /testsuite/synth/sns01/tb_unaries.vhdl
parentb65433877b2e1cb6053f0c9821719c882bcb9ea8 (diff)
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testsuite/synth: add more tests for std_logic_arith
Diffstat (limited to 'testsuite/synth/sns01/tb_unaries.vhdl')
-rw-r--r--testsuite/synth/sns01/tb_unaries.vhdl65
1 files changed, 65 insertions, 0 deletions
diff --git a/testsuite/synth/sns01/tb_unaries.vhdl b/testsuite/synth/sns01/tb_unaries.vhdl
new file mode 100644
index 000000000..282ac0355
--- /dev/null
+++ b/testsuite/synth/sns01/tb_unaries.vhdl
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_unaries is
+end;
+
+architecture behav of tb_unaries is
+ type sl_map_type is array (std_ulogic) of character;
+ constant sl_map : sl_map_type := "UX01ZWLH-";
+
+ function to_string(v : std_logic_vector) return string
+ is
+ alias av : std_logic_vector(1 to v'length) is v;
+ variable res : string (1 to v'length);
+ begin
+ for i in res'range loop
+ res (i) := sl_map (av (i));
+ end loop;
+ return res;
+ end to_string;
+
+ signal li : integer;
+ signal l4 : std_logic_vector (3 downto 0);
+ signal plus_u4u : std_logic_vector (3 downto 0);
+ signal plus_s4s : std_logic_vector (3 downto 0);
+ signal minus_s4s : std_logic_vector (3 downto 0);
+ signal abs_s4s : std_logic_vector (3 downto 0);
+ signal plus_u4v : std_logic_vector (3 downto 0);
+ signal plus_s4v : std_logic_vector (3 downto 0);
+ signal minus_s4v : std_logic_vector (3 downto 0);
+ signal abs_s4v : std_logic_vector (3 downto 0);
+begin
+ dut: entity work.unaries
+ port map (
+ l4 => l4,
+ plus_u4u => plus_u4u,
+ plus_s4s => plus_s4s,
+ minus_s4s => minus_s4s,
+ abs_s4s => abs_s4s,
+
+ plus_u4v => plus_u4v,
+ plus_s4v => plus_s4v,
+ minus_s4v => minus_s4v,
+ abs_s4v => abs_s4v);
+
+ process
+ begin
+ for i in -8 to 7 loop
+ li <= i;
+ l4 <= conv_std_logic_vector (i, 4);
+ wait for 1 ns;
+ report "u4u: + " & integer'image(i) & " = " & to_string(plus_u4u);
+ report "s4s: + " & integer'image(i) & " = " & to_string(plus_s4s);
+ report "s4s: - " & integer'image(i) & " = " & to_string(minus_s4s);
+ report "s4s: abs " & integer'image(i) & " = " & to_string(abs_s4s);
+
+ report "u4v: + " & integer'image(i) & " = " & to_string(plus_u4v);
+ report "s4v: + " & integer'image(i) & " = " & to_string(plus_s4v);
+ report "s4v: - " & integer'image(i) & " = " & to_string(minus_s4v);
+ report "s4v: abs " & integer'image(i) & " = " & to_string(abs_s4v);
+ end loop;
+ wait;
+ end process;
+end behav;