testsuite/synth: add testcase for slice of slice.

3 files changed, 39 insertions, 1 deletions

diff --git a/testsuite/synth/slice01/slice03.vhdl b/testsuite/synth/slice01/slice03.vhdl
new file mode 100644
index 000000000..0509efcbf
--- /dev/null
+++ b/testsuite/synth/slice01/slice03.vhdl
@@ -0,0 +1,12 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity slice03 is
+  port (di : std_logic_vector(7 downto 0);
+        do : out std_logic_vector (3 downto 0));
+end slice03;
+
+architecture behav of slice03 is
+begin
+  do <= di (7 downto 4)(7 downto 4);
+end behav;
diff --git a/testsuite/synth/slice01/tb_slice03.vhdl b/testsuite/synth/slice01/tb_slice03.vhdl
new file mode 100644
index 000000000..a1e92cfe8
--- /dev/null
+++ b/testsuite/synth/slice01/tb_slice03.vhdl
@@ -0,0 +1,26 @@
+entity tb_slice03 is
+end tb_slice03;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_slice03 is
+  signal di : std_logic_vector (7 downto 0);
+  signal do : std_logic_vector (3 downto 0);
+begin
+  dut: entity work.slice03
+    port map (di, do);
+
+  process
+  begin
+    di <= x"12";
+    wait for 1 ns;
+    assert do = x"1" severity error;
+    
+    di <= x"e5";
+    wait for 1 ns;
+    assert do = x"e" severity error;
+    
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/slice01/testsuite.sh b/testsuite/synth/slice01/testsuite.sh
index 0220769ab..dcaf3f202 100755
--- a/testsuite/synth/slice01/testsuite.sh
+++ b/testsuite/synth/slice01/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in slice01 slice02; do
+for t in slice01 slice02 slice03; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean