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| author | Tristan Gingold <tgingold@free.fr> | 2019-08-15 05:39:58 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-08-15 10:00:08 +0200 |
| commit | b2b8a8f6c3389ca2764fa22149e68b9b1faae6a6 (patch) | |
| tree | 8019a8563f8dfae173a9f74f7332a6a4f065ce7a /testsuite/synth/psl01 | |
| parent | f7f0f0a48f49e0328401c1f60575f07c92c0c15f (diff) | |
| download | ghdl-b2b8a8f6c3389ca2764fa22149e68b9b1faae6a6.tar.gz ghdl-b2b8a8f6c3389ca2764fa22149e68b9b1faae6a6.tar.bz2 ghdl-b2b8a8f6c3389ca2764fa22149e68b9b1faae6a6.zip | |
testsuite/synth: fix assert1 assertion.
Diffstat (limited to 'testsuite/synth/psl01')
| -rw-r--r-- | testsuite/synth/psl01/assert1.vhdl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/testsuite/synth/psl01/assert1.vhdl b/testsuite/synth/psl01/assert1.vhdl index 13e44a1e8..717b4d0f9 100644 --- a/testsuite/synth/psl01/assert1.vhdl +++ b/testsuite/synth/psl01/assert1.vhdl @@ -23,5 +23,5 @@ begin cnt <= val; --psl default clock is rising_edge(clk); - --psl assert always val /= 5 or rst = '1'; + --psl assert always val /= 5 abort rst; end behav; |