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authorTristan Gingold <tgingold@free.fr>2020-01-13 06:20:37 +0100
committerTristan Gingold <tgingold@free.fr>2020-01-13 06:20:37 +0100
commit060f60ec7c5ce23cea3ec985c8921fcf104ad872 (patch)
treed82ce68af41b657662b2a7b05d212d28fffb034f /testsuite/synth/oper01
parentbcc88a45ddffd2cc54b9fcbfe7313f624478f873 (diff)
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testsuite/synth: add a test for static unsigned "-". For #1087
Diffstat (limited to 'testsuite/synth/oper01')
-rw-r--r--testsuite/synth/oper01/tb_uns01.vhdl20
-rwxr-xr-xtestsuite/synth/oper01/testsuite.sh2
-rw-r--r--testsuite/synth/oper01/uns01.vhdl19
3 files changed, 40 insertions, 1 deletions
diff --git a/testsuite/synth/oper01/tb_uns01.vhdl b/testsuite/synth/oper01/tb_uns01.vhdl
new file mode 100644
index 000000000..36bb51b1b
--- /dev/null
+++ b/testsuite/synth/oper01/tb_uns01.vhdl
@@ -0,0 +1,20 @@
+entity tb_uns01 is
+end tb_uns01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_uns01 is
+ signal r : boolean;
+begin
+ cmp01_1: entity work.uns01
+ port map (r);
+
+ process
+ begin
+ wait for 1 ns;
+ assert r severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/oper01/testsuite.sh b/testsuite/synth/oper01/testsuite.sh
index b6695ca28..d91a4e941 100755
--- a/testsuite/synth/oper01/testsuite.sh
+++ b/testsuite/synth/oper01/testsuite.sh
@@ -2,7 +2,7 @@
. ../../testenv.sh
-for t in snum01 snum02 snum03 snum04 snum05 cmp01 cmp02 match01; do
+for t in snum01 snum02 snum03 snum04 snum05 cmp01 cmp02 match01 uns01; do
analyze $t.vhdl tb_$t.vhdl
elab_simulate tb_$t --ieee-asserts=disable-at-0
clean
diff --git a/testsuite/synth/oper01/uns01.vhdl b/testsuite/synth/oper01/uns01.vhdl
new file mode 100644
index 000000000..df75755ca
--- /dev/null
+++ b/testsuite/synth/oper01/uns01.vhdl
@@ -0,0 +1,19 @@
+entity uns01 is
+ port (ok : out boolean);
+end uns01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of uns01 is
+ -- add uns uns
+ constant a : unsigned (7 downto 0) := x"1e";
+ constant b : unsigned (3 downto 0) := x"2";
+ constant r1 : unsigned (7 downto 0) := a - b;
+ signal er1 : unsigned (7 downto 0);
+begin
+ er1 <= x"1c";
+-- ok <= r1 = x"20";
+ ok <= r1 = er1;
+end behav;