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authorTristan Gingold <tgingold@free.fr>2022-04-27 09:46:49 +0200
committerTristan Gingold <tgingold@free.fr>2022-04-27 09:46:49 +0200
commit630b01519388cbda2929ccb1928f20806dc8ee17 (patch)
treec4b919c079324b7bff30003fd5e5486e7cd92228 /testsuite/synth/memmux01
parent7fdbe576eb04ea5a6015a17caa0b87d8810452fe (diff)
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synth-vhdl_stmts: add implicit conversion for cond assignment
Fix #2042 (The first issue only)
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