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| author | Tristan Gingold <tgingold@free.fr> | 2020-02-18 18:44:42 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-02-18 18:45:07 +0100 |
| commit | 393612fc52586d8eb8372f0ce3f05c162cfccfe2 (patch) | |
| tree | 9a3f06bd59ba01c80b8012b1e3e52e7a4aa516d9 /testsuite/synth/mem2d01 | |
| parent | 3689e0eb1d8b4a9689afa6f76187f1ecdc5ec458 (diff) | |
| download | ghdl-393612fc52586d8eb8372f0ce3f05c162cfccfe2.tar.gz ghdl-393612fc52586d8eb8372f0ce3f05c162cfccfe2.tar.bz2 ghdl-393612fc52586d8eb8372f0ce3f05c162cfccfe2.zip | |
testsuite/synth: merge ram01 to mem01, add NOTES.txt
Diffstat (limited to 'testsuite/synth/mem2d01')
| -rw-r--r-- | testsuite/synth/mem2d01/NOTES.txt | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/testsuite/synth/mem2d01/NOTES.txt b/testsuite/synth/mem2d01/NOTES.txt new file mode 100644 index 000000000..17ed281fb --- /dev/null +++ b/testsuite/synth/mem2d01/NOTES.txt @@ -0,0 +1,7 @@ +Tests for RAMs +-------------- + +dpram1r: Read(2d)+Write(1d), using indexes +dpram2r: Read(2d)+Write(1d), using slices. +dpram2w: Read(1d)+Write(2d), using slices. +memmux04: Read(2d)+Write(1d), enable on write, intermediate variable for read. |