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authorTristan Gingold <tgingold@free.fr>2020-03-09 07:50:10 +0100
committerTristan Gingold <tgingold@free.fr>2020-03-09 07:50:10 +0100
commit8a5f4cc621ddd4f280f85474c6cc9b33344aec66 (patch)
tree9f8d225e785728996e2b3740bd37337c8d799028 /testsuite/synth/match01
parentcb5c549a6e199fa55ebf1f8030f674bc50c59e2b (diff)
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testsuite/synth: add a testcase for previous commit.
Diffstat (limited to 'testsuite/synth/match01')
-rw-r--r--testsuite/synth/match01/match01.vhdl12
-rw-r--r--testsuite/synth/match01/match02.vhdl12
-rw-r--r--testsuite/synth/match01/tb_match01.vhdl34
-rw-r--r--testsuite/synth/match01/tb_match02.vhdl34
-rwxr-xr-xtestsuite/synth/match01/testsuite.sh10
5 files changed, 102 insertions, 0 deletions
diff --git a/testsuite/synth/match01/match01.vhdl b/testsuite/synth/match01/match01.vhdl
new file mode 100644
index 000000000..8deb92752
--- /dev/null
+++ b/testsuite/synth/match01/match01.vhdl
@@ -0,0 +1,12 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity match01 is
+ port (a : in std_logic_vector (3 downto 0);
+ z : out std_logic);
+end match01;
+
+architecture behav of match01 is
+begin
+ z <= a ?= "1--0";
+end behav;
diff --git a/testsuite/synth/match01/match02.vhdl b/testsuite/synth/match01/match02.vhdl
new file mode 100644
index 000000000..f20904f0a
--- /dev/null
+++ b/testsuite/synth/match01/match02.vhdl
@@ -0,0 +1,12 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity match02 is
+ port (a : in std_logic_vector (3 downto 0);
+ z : out std_logic);
+end match02;
+
+architecture behav of match02 is
+begin
+ z <= a ?/= "1--0";
+end behav;
diff --git a/testsuite/synth/match01/tb_match01.vhdl b/testsuite/synth/match01/tb_match01.vhdl
new file mode 100644
index 000000000..88268b205
--- /dev/null
+++ b/testsuite/synth/match01/tb_match01.vhdl
@@ -0,0 +1,34 @@
+entity tb_match01 is
+end tb_match01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_match01 is
+ signal a : std_logic_vector(3 downto 0);
+ signal z : std_logic;
+begin
+ dut: entity work.match01
+ port map (a, z);
+
+ process
+ begin
+ a <= "1000";
+ wait for 1 ns;
+ assert z = '1' severity failure;
+
+ a <= "1010";
+ wait for 1 ns;
+ assert z = '1' severity failure;
+
+ a <= "0000";
+ wait for 1 ns;
+ assert z = '0' severity failure;
+
+ a <= "0001";
+ wait for 1 ns;
+ assert z = '0' severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/match01/tb_match02.vhdl b/testsuite/synth/match01/tb_match02.vhdl
new file mode 100644
index 000000000..52074709f
--- /dev/null
+++ b/testsuite/synth/match01/tb_match02.vhdl
@@ -0,0 +1,34 @@
+entity tb_match02 is
+end tb_match02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_match02 is
+ signal a : std_logic_vector(3 downto 0);
+ signal z : std_logic;
+begin
+ dut: entity work.match02
+ port map (a, z);
+
+ process
+ begin
+ a <= "1000";
+ wait for 1 ns;
+ assert z = '0' severity failure;
+
+ a <= "1010";
+ wait for 1 ns;
+ assert z = '0' severity failure;
+
+ a <= "0000";
+ wait for 1 ns;
+ assert z = '1' severity failure;
+
+ a <= "0001";
+ wait for 1 ns;
+ assert z = '1' severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/match01/testsuite.sh b/testsuite/synth/match01/testsuite.sh
new file mode 100755
index 000000000..a0e43259e
--- /dev/null
+++ b/testsuite/synth/match01/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+for t in match01 match02; do
+ synth_tb $t
+done
+
+echo "Test successful"