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authorTristan Gingold <tgingold@free.fr>2019-10-01 20:29:13 +0200
committerTristan Gingold <tgingold@free.fr>2019-10-01 20:29:13 +0200
commit2e12aa8732cd49438a165a0b20c9acd9e37cde4d (patch)
tree214007f9320397a9336680613024f809d45d3501 /testsuite/synth/issue958/ent1.vhdl
parent8de90a32fbbdea13cd1269f9c3769a11487520f1 (diff)
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testsuite/synth: add testcases for #958
Diffstat (limited to 'testsuite/synth/issue958/ent1.vhdl')
-rw-r--r--testsuite/synth/issue958/ent1.vhdl21
1 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/synth/issue958/ent1.vhdl b/testsuite/synth/issue958/ent1.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent1 is
+end;
+
+architecture a of ent1 is
+ component c is
+ port (
+ p : in std_logic_vector(7 downto 0)
+ );
+ end component;
+ signal s : std_logic_vector(7 downto 0);
+begin
+ inst: component c
+ port map (
+ p => s
+ );
+ s <= x"01";
+end;
+