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author | Tristan Gingold <tgingold@free.fr> | 2019-10-01 20:29:13 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-01 20:29:13 +0200 |
commit | 2e12aa8732cd49438a165a0b20c9acd9e37cde4d (patch) | |
tree | 214007f9320397a9336680613024f809d45d3501 /testsuite/synth/issue958/ent.vhdl | |
parent | 8de90a32fbbdea13cd1269f9c3769a11487520f1 (diff) | |
download | ghdl-2e12aa8732cd49438a165a0b20c9acd9e37cde4d.tar.gz ghdl-2e12aa8732cd49438a165a0b20c9acd9e37cde4d.tar.bz2 ghdl-2e12aa8732cd49438a165a0b20c9acd9e37cde4d.zip |
testsuite/synth: add testcases for #958
Diffstat (limited to 'testsuite/synth/issue958/ent.vhdl')
-rw-r--r-- | testsuite/synth/issue958/ent.vhdl | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/testsuite/synth/issue958/ent.vhdl b/testsuite/synth/issue958/ent.vhdl new file mode 100644 index 000000000..8926ae673 --- /dev/null +++ b/testsuite/synth/issue958/ent.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is +end; + +architecture a of ent is + component c is + port ( + p : in std_logic_vector(7 downto 0) + ); + end component; +begin + inst: component c + port map ( + p => x"00" + ); +end; + |