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author | Tristan Gingold <tgingold@free.fr> | 2019-09-30 01:13:08 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-30 01:13:08 +0200 |
commit | 108c48221f7a367b2b33499b469eab0afcaafd43 (patch) | |
tree | ccd79dc03b6f6e743b8de9739a3a10487ac70f06 /testsuite/synth/issue948 | |
parent | e87a1678e51b22db4d153ed7237a4cfa76d6ee9e (diff) | |
download | ghdl-108c48221f7a367b2b33499b469eab0afcaafd43.tar.gz ghdl-108c48221f7a367b2b33499b469eab0afcaafd43.tar.bz2 ghdl-108c48221f7a367b2b33499b469eab0afcaafd43.zip |
testsuite/synth: add testcase for #948
Diffstat (limited to 'testsuite/synth/issue948')
-rw-r--r-- | testsuite/synth/issue948/ent.vhdl | 22 | ||||
-rwxr-xr-x | testsuite/synth/issue948/testsuite.sh | 11 |
2 files changed, 33 insertions, 0 deletions
diff --git a/testsuite/synth/issue948/ent.vhdl b/testsuite/synth/issue948/ent.vhdl new file mode 100644 index 000000000..a2f7aadb9 --- /dev/null +++ b/testsuite/synth/issue948/ent.vhdl @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + port ( + i : in bit; + o : out bit + ); +end; + +architecture a of ent is + signal test : std_logic_vector(7 downto 0); + alias a : std_logic_vector(7 downto 0) is test; +begin + process(i) + begin + if a = x"00" then + end if; + + o <= i; + end process; +end; diff --git a/testsuite/synth/issue948/testsuite.sh b/testsuite/synth/issue948/testsuite.sh new file mode 100755 index 000000000..54e687d28 --- /dev/null +++ b/testsuite/synth/issue948/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +for f in ent; do + synth $f.vhdl -e $f > syn_$f.vhdl +# analyze syn_$f.vhdl +done +clean + +echo "Test successful" |