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author | Tristan Gingold <tgingold@free.fr> | 2019-08-08 05:28:17 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-08-08 05:28:17 +0200 |
commit | 6e51ccf3b2875a6b4e7ba1b7215b0ec28f0655b6 (patch) | |
tree | 73b24e91fe6f8a6874785e1fea5b7853c70ab0dc /testsuite/synth/issue872/alu.vhdl | |
parent | 1a0606c144230040143e8080016302bc51a48bfb (diff) | |
download | ghdl-6e51ccf3b2875a6b4e7ba1b7215b0ec28f0655b6.tar.gz ghdl-6e51ccf3b2875a6b4e7ba1b7215b0ec28f0655b6.tar.bz2 ghdl-6e51ccf3b2875a6b4e7ba1b7215b0ec28f0655b6.zip |
synth: add testcase from #872
Diffstat (limited to 'testsuite/synth/issue872/alu.vhdl')
-rw-r--r-- | testsuite/synth/issue872/alu.vhdl | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/testsuite/synth/issue872/alu.vhdl b/testsuite/synth/issue872/alu.vhdl new file mode 100644 index 000000000..19139792d --- /dev/null +++ b/testsuite/synth/issue872/alu.vhdl @@ -0,0 +1,42 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity alu is + port ( + clk : in std_logic; + rst : in std_logic; + opcode : in std_logic_vector(15 downto 0); + a : in std_logic; + b : in std_logic; + y : out std_logic + ); +end alu; + +architecture mux of alu is + signal ci : std_logic; + signal co : std_logic; + signal mux1, mux2: std_logic_vector(7 downto 0); +begin + + process(a, b, ci, mux1, mux2) + variable sel : unsigned(2 downto 0); + begin + sel := a & b & ci; + y <= mux1(to_integer(sel)); + co <= mux2(to_integer(sel)); + end process; + + process(clk, rst) + begin + if(rst = '0') then + ci <= '0'; + mux1 <= (others => '0'); + mux2 <= (others => '0'); + elsif(rising_edge(clk)) then + ci <= co; + mux1 <= opcode(15 downto 8); + mux2 <= opcode(7 downto 0); + end if; + end process; +end mux; |